SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR REDUCING MEMORY WRITE OPERATIONS USING DIFFERENCE INFORMATION

• US 20080126724A1
• Filed: 09/07/2007
• Published: 05/29/2008
• Est. Priority Date: 11/24/2006
• Status: Active Grant

• Current Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Original Assignee: SandForce, Inc. (Broadcom, Inc.)
• Inventors: Danilak, Radoslav
• Granted Patent: US 7,904,619 B2
• Time in Patent Office: Days
• US Class Current: 711/162
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0656 Data buffering arrangements
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically

Abstract

A system, method, and computer program product are provided for reducing write operations in memory. In use, write operations to be performed on data stored in memory are identified. A difference is then determined between results of the write operations and the data stored in the memory. Difference information associated with the difference is stored in the memory. To this end, the write operations may be reduced, utilizing the difference information.

Claims

1. A method, comprising:

identifying write operations to be performed on data stored in memory;

determining a difference between results of the write operations and the data stored in the memory;

storing difference information associated with the difference in the memory; and

reducing the write operations, utilizing the difference information.

2. The method of claim 1, wherein the difference information is compressed.

3. The method of claim 1, wherein, in response to a read operation, the data and the difference information are retrieved, and the data is reconstructed utilizing the difference information.

4. The method of claim 3, wherein the difference information is retrieved from the memory.

5. The method of claim 3, wherein the difference information is retrieved from a buffer.

6. The method of claim 1, wherein the difference information is stored in a buffer.

7. The method of claim 6, wherein, in response to the buffer being full, the difference information is stored in the memory.

8. The method of claim 1, wherein the difference information is stored in a block of the memory in which corresponding data is stored.

9. The method of claim 8, wherein the difference information is stored in a portion of the block having a predetermined size.

10. The method of claim 9, wherein the predetermined size is user configured.

11. The method of claim 9, wherein, in response to the difference information exceeding the predetermined size, the data and the difference information is retrieved from the block, the data is reconstructed utilizing the difference information, and the reconstructed data is stored in the block.

12. The method of claim 1, wherein the difference information is stored utilizing an instruction set.

13. The method of claim 12, wherein the instruction set dynamically expands.

14. The method of claim 12, wherein the instruction set adaptively changes.

15. The method of claim 1, wherein the difference is determined on a byte-by-byte basis.

16. The method of claim 1, wherein the difference is determined utilizing data motion estimation.

17. The method of claim 1, wherein the memory includes a mechanical storage device.

18. The method of claim 15, wherein the memory includes a disk drive.

19. The method of claim 1, wherein the memory includes a volatile memory device.

20. The method of claim 1, wherein the memory includes a nonvolatile memory device.

21. The method of claim 20, wherein the nonvolatile memory device includes at least one of single-bit per cell NOR flash memory, multi-bit per cell NOR flash memory, single-bit per cell NAND flash memory, and multi-bit per cell NAND flash memory.

22. A computer program product embodied on a computer readable medium, comprising:

computer code for identifying write operations to be performed on data stored in memory;

computer code for determining a difference between results of the write operations and the data stored in the memory;

computer code for storing difference information associated with the difference in the memory; and

computer code for reducing the write operations, utilizing the difference information.

23. An apparatus, comprising:

a difference computation module for determining a difference between results of write operations to be performed on data stored in memory and the data stored in the memory, where difference information associated with the difference is stored in the memory;

an update module in communication with the difference computation module, the update module for reducing the write operations, utilizing the difference information.

24. The apparatus of claim 23, wherein the apparatus is coupled between a system and the memory.

25. The apparatus of claim 23, wherein the controller is coupled between a system and secondary storage.