DIE STACKING USING INSULATED WIRE BONDS

• US 20080128880A1
• Filed: 03/30/2007
• Published: 06/05/2008
• Est. Priority Date: 12/01/2006
• Status: Abandoned Application

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Inventors: Takiar, Hem, Bhagath, Shrikar
• Application Number:
  US11/694,713
• Publication Number:
  US 20080128880A1
• Time in Patent Office: Days
• US Class Current: 257/686
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/2929 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/29299 Base material
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/45147 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/4554 Coating
• CPC Class Codes: H01L 2224/45565 Single coating layer
• CPC Class Codes: H01L 2224/4569 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48175 the item being metallic
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/48471 the other connecting portion not on the bonding area being a ball bond, i.e. wedge-to-ball, reverse stitch
• CPC Class Codes: H01L 2224/48599 Principal constituent of the connecting portion of the wire connector being Gold (Au)
• CPC Class Codes: H01L 2224/48699 Principal constituent of the connecting portion of the wire connector being Aluminium (Al)
• CPC Class Codes: H01L 2224/48992 Reinforcing structures
• CPC Class Codes: H01L 2224/49175 : Parallel arrangements
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 2224/78 : Apparatus for connecting with wire connectors
• CPC Class Codes: H01L 2224/8314 : Guiding structures outside the body
• CPC Class Codes: H01L 2224/83191 : wherein the layer connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/83192 : wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/83194 : Lateral distribution of the layer connectors
• CPC Class Codes: H01L 2224/8385 : using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
• CPC Class Codes: H01L 2224/83856 : Pre-cured adhesive, i.e. B-stage adhesive
• CPC Class Codes: H01L 2224/83862 : Heat curing
• CPC Class Codes: H01L 2224/83874 : Ultraviolet [UV] curing
• CPC Class Codes: H01L 2224/85186 : connecting first outside the semiconductor or solid-state body, i.e. off-chip, reverse stitch
• CPC Class Codes: H01L 2224/85399 : Material
• CPC Class Codes: H01L 2224/8592 : Applying permanent coating, e.g. protective coating
• CPC Class Codes: H01L 2224/92 : Specific sequence of method steps
• CPC Class Codes: H01L 2224/92247 : the second connecting process involving a wire connector
• CPC Class Codes: H01L 2225/0651 : Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/33 : of a plurality of layer connectors
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/85 : using a wire connector wire bonding in general B23K20/004
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 : Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/0665 : Epoxy resin
• CPC Class Codes: H01L 2924/07802 : not being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1433 : Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

A low profile semiconductor package is disclosed including at least first and second stacked semiconductor die mounted to a substrate. The first and second semiconductor die are separated by a low profile intermediate adhesive layer. After the intermediate layer is applied, the second semiconductor die may be stacked on top of the intermediate layer. The first semiconductor layer may be wire-bonded to the substrate using bond wires sheathed within an electrical insulator. As the bond wires are surrounded by an electrical insulator, the intermediate layer need not space the wire bond loops from the second semiconductor die as in the prior art, and the apex of bond wires may come into contact with the dielectric layer. The intermediate layer may thus be made thinner in comparison to conventional stacked semiconductor die configurations.

Claims

1. A semiconductor device, comprising:

a first semiconductor die including first and second opposed surfaces, the first surface including a plurality of bond pads;

a plurality of bond wires, each bond wire of the plurality of bond wires sheathed in an electrical insulator and having an end affixed to a bond pad of the first semiconductor die;

an intermediate layer applied to the first surface of the first semiconductor die; and

a second semiconductor die, the electrical insulator around the bond wires provided to prevent electrical coupling between the plurality of bond wires and the second semiconductor die.

2. A semiconductor device as recited in claim 1, wherein the intermediate layer is a rigid spacer layer.

3. A semiconductor device as recited in claim 1, wherein the intermediate layer is a liquid layer.

4. A semiconductor device as recited in claim 3, wherein the plurality of bond wires are embedded within the intermediate layer.

5. A semiconductor device as recited in claim 3, wherein the plurality of bond wires are spaced from the intermediate layer.

6. A semiconductor device as recited in claim 1, wherein the electrical insulator within which the bond wires are sheathed is formed of one of a polyimide and a polyester.

7. A semiconductor device as recited in claim 1, wherein the intermediate layer covers a first area on the first surface including the bond wires and not covering a second area of the first surface not including the bond wires.

8. A semiconductor device as recited in claim 1, wherein the intermediate layer is an adhesive layer for affixing the first and second semiconductor die together.

9. A semiconductor device as recited in claim 1, wherein the intermediate layer is an epoxy layer for affixing the first and second semiconductor die together.

10. A semiconductor device as recited in claim 1, wherein the bond wires are affixed to the first semiconductor die in a bond loop shape, the intermediate layer having a height above the first surface of the first semiconductor die approximately equal to a height of an uppermost portion of the bond loops above the first surface of the first semiconductor die.

11. A semiconductor device as recited in claim 1, wherein the plurality of bond wires are provided adjacent a single edge of the first surface of the first semiconductor die.

12. A semiconductor device as recited in claim 1, wherein the plurality of bond wires are provided along two or more edges of the first surface of the first semiconductor die.

13. A semiconductor device as recited in claim 1, wherein the semiconductor device is a flash memory device.

14. A semiconductor device as recited in claim 1, wherein the intermediate layer includes a plurality of spacer balls.

15. A semiconductor device, comprising:

a first semiconductor die including first and second opposed surfaces, the first surface including a plurality of bond pads;

a plurality of bond wires, each bond wire of the plurality of bond wires having an end affixed to a bond pad of the first semiconductor die and forming a bond loop;

an electrical insulator within which the plurality of bond wires are sheathed;

an adhesive layer applied to the first surface of the first semiconductor die, at least a portion of the bond loop for each of the plurality of bond wires embedded within the adhesive layer;

a second semiconductor die affixed to the adhesive layer; and

an electrical insulating layer interposed between the second semiconductor die and the adhesive layer, the electrical insulator within which the plurality of bond wires are sheathed electrically insulating the second semiconductor die from the bond wires in the adhesive layer.

16. A semiconductor device as recited in claim 15, wherein the intermediate layer is a rigid spacer layer.

17. A semiconductor device as recited in claim 15, wherein the intermediate layer is a liquid layer.

18. A semiconductor device as recited in claim 17, wherein the plurality of bond wires are embedded within the intermediate layer.

19. A semiconductor device as recited in claim 17, wherein the plurality of bond wires are spaced from the intermediate layer.

20. A semiconductor device as recited in claim 15, wherein the electrical insulator within which the bond wires are sheathed is formed of one of a polyimide and a polyester.

21. A semiconductor device as recited in claim 15, wherein the adhesive layer is an epoxy.

22. A semiconductor device, comprising:

a first semiconductor die including first and second opposed surfaces, the first surface including a plurality of bond pads;

a plurality of bond wires, each bond wire of the plurality of bond wires having an end affixed to a bond pad of the first semiconductor die and forming a bond loop;

an electrical insulator within which the plurality of bond wires are sheathed;

an adhesive layer applied to the first surface of the first semiconductor die, at least a portion of the bond loop for each of the plurality of bond wires embedded within the adhesive layer;

a second semiconductor die affixed to the adhesive layer; and

an electrical insulating layer interposed between the second semiconductor die and the adhesive layer, the semiconductor package formed by the steps of;

(a) wire bonding a plurality of wires to a surface of the first semiconductor die to form a plurality of wire bond loops;

(b) forming the intermediate layer on the surface of the first semiconductor die receiving the plurality of wires in said step (a);

(c) affixing the second semiconductor die to the first semiconductor die;

(d) reducing a thickness of the intermediate layer under a compressive force exerted on the intermediate layer by the first and second semiconductor die; and

(e) preventing the plurality of wires from electrically coupling with the second semiconductor die by sheathing the plurality of bond wires in an electrical insulator.

23. A semiconductor package as recited in claim 22, wherein the electrical insulation around the bond wires is formed by passing the wires through a liquid solution of the electrical insulation.

24. A semiconductor package as recited in claim 22, wherein the electrical insulation around the bond wires is formed by spraying a liquid solution of the electrical insulation onto the wires.