SEMICONDUCTOR CHIP AND TAB PACKAGE HAVING THE SAME

• US 20080128902A1
• Filed: 01/09/2008
• Published: 06/05/2008
• Est. Priority Date: 11/26/2004
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: CHUNG, Ye-Chung, KANG, Sa-Yoon, KIM, Dong-Han
• Granted Patent: US 7,732,933 B2
• Time in Patent Office: Days
• US Class Current: 257/735
• CPC Class Codes: H01L 21/4839 Assembly of a flat lead with an insulating support, e.g. for TAB
• CPC Class Codes: H01L 2224/0554 External layer
• CPC Class Codes: H01L 2224/0555 Shape
• CPC Class Codes: H01L 2224/0556 Disposition
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/06051 Bonding areas having different shapes
• CPC Class Codes: H01L 2224/0615 Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
• CPC Class Codes: H01L 2224/0616 Random array, i.e. array with no symmetry
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 23/49572 consisting of thin flexible metallic tape with or without a film carrier H01L23/49503 - H01L23/49568 and H01L23/49575 - H01L23/49579 take precedence
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 23/4985 Flexible insulating substrates H01L23/49572 and H01L23/49855 take precedence
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/17 : of a plurality of bump connectors
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

A semiconductor chip, having an active surface including a peripheral area and a central area, presents a connection area formed on a portion of the peripheral area. The semiconductor chip includes output pads formed in the peripheral area of the active surface and input pads formed in the central area of the active surface. The input pads may be connected to wiring patterns of a TAB tape passing over the connection area.

Claims

1. A semiconductor chip comprising:

an active surface having two long sides and two short sides;

a plurality of output pads disposed along the two long sides and two short sides of the active surface; and

a plurality of input pads disposed on the active surface, wherein at least one of the input pads is farther from the nearest long side and short side than a nearest output pad.

2. The semiconductor chip of claim 1, wherein the plurality of input pads comprise a power pad and a ground pad.

3. The semiconductor chip of claim 2, wherein the plurality of input pads comprise a plurality of signal pads.

4. The semiconductor chip of claim 3, wherein the plurality of input pads are symmetric with respect to a center of the long side of the active surface.

5. The semiconductor chip of claim 3, wherein a distance from the short side of an outermost input pad of the plurality of input pads is longer than a distance from the long side of the outermost input pad of the plurality of input pads.

6. The semiconductor chip of claim 1, further comprising:

a dummy pad disposed on the active surface.

7. The semiconductor chip of claim 6, wherein the dummy pad located on substantially same imaginary line with respect to the output pads through at least one side of the active surface.

8. The semiconductor chip of claim 7, wherein the at least one side is the long side of the active surface.

15. The semiconductor package of claim 8, further comprising:

a dummy bump disposed on the active surface.

16. The semiconductor package of claim 15, wherein the dummy bump located on substantially same imaginary line with respect to the output bumps through at least one side of the active surface.

17. The semiconductor package of claim 16, wherein the at least one side is the long side of the active surface.

9. A semiconductor package comprising:

a (film) substrate;

a semiconductor chip disposed on the substrate, the semiconductor chip comprising;

an active surface having two long sides and two short sides;

a plurality of output bumps disposed along the two long sides and two short sides of the active surface;

a plurality of input bumps disposed on the active surface, wherein at least one of the input bumps is farther from the nearest long side and short side than a nearest output bump;

wiring patterns coupled to the bumps and disposed on the substrate.

10. The semiconductor package of claim 9, further comprising:

output terminal patterns electrically coupled to the output bumps through the wiring patterns;

input terminal patterns electrically coupled to the input bumps through the wiring patterns.

11. The semiconductor package of claim 10, wherein the semiconductor package is a tape automated bonding package.

12. The semiconductor package of claim 11, wherein the plurality of input bumps comprise a power bump and a ground bump.

13. The semiconductor package of claim 12, wherein the plurality of input bumps comprise a signal pad.

14. The semiconductor package of claim 12, wherein the plurality of input bumps are symmetric with respect to a center of the long side of the active surface.

18. The semiconductor package of claim 9, wherein the wiring patterns are disposed over the active surface, the wiring patterns have at least one bent portion.

19. The semiconductor package of claim 9, wherein the plurality of input bumps comprise a power bump and a ground bump.

20. The semiconductor chip of claim 9, wherein a distance from the short side of an outermost input bumps of the plurality of input bumps is longer than a distance from the long side of the outermost input bump of the plurality of input bumps.