Post Passivation Interconnection Process And Structures

• US 20080128910A1
• Filed: 01/16/2008
• Published: 06/05/2008
• Est. Priority Date: 09/09/2004
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Lin, Mou-Shiung, Chou, Chien-Kang, Chou, Chiu-Ming
• Granted Patent: US 8,018,060 B2
• Time in Patent Office: Days
• US Class Current: 257/758
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/13022 the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 23/3171 the coating being directly applied to the semiconductor body, e.g. passivation layer H01L23/3178 takes precedence
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/5228 Resistive arrangements or effects of, or between, wiring layers other resistive arrangements H01L23/647
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/04953 TaN
• CPC Class Codes: H01L 2924/05042 Si3N4
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/19015 including thin film passive components
• CPC Class Codes: H01L 2924/19041 being a capacitor
• CPC Class Codes: H01L 2924/19042 being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/19104 : on the semiconductor or solid-state device, i.e. passive-on-chip
• CPC Class Codes: H01L 2924/30105 : Capacitance

Abstract

A system and method for forming post passivation metal structures is described. Metal interconnections and high quality electrical components, such as inductors, transformers, capacitors, or resistors are formed on a layer of passivation, or on a thick layer of polymer over a passivation layer.

Claims

1. An integrated circuit structure comprising:

a silicon substrate;

a transistor in and on said silicon substrate;

a first dielectric layer over said silicon substrate;

a metallization structure over said first dielectric layer, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer;

a second dielectric layer over said first dielectric layer and between said first and second metal layers, wherein said second dielectric layer has a thickness between 0.1 and 1 micrometer;

a metal trace over said first dielectric layer;

a contact pad over said silicon substrate;

a passivation layer over said metallization structure, over said first and second dielectric layers, over said metal trace and over said first and second metal layers, wherein a first opening in said passivation layer is over said contact pad and exposes said contact pad, wherein said passivation layer comprises an oxide layer and a nitride layer;

a polymer layer on said passivation layer, wherein said polymer layer has a thickness between 2 and 150 micrometers and greater than that of said passivation layer, wherein a second opening in said polymer layer is over said contact pad and exposes said contact pad and said passivation layer, wherein said second opening has a transverse dimension, from a cross-sectional view, greater than that of said first opening, wherein said polymer layer comprises polyimide;

a coil on said polymer layer, wherein said coil comprises a glue/barrier layer on said polymer layer, a seed layer comprising a first copper layer having a thickness between 0.2 and 1 micrometer on said glue/barrier layer and over said polymer layer, and an electroplated metal layer comprising a second copper layer having a thickness between 3 and 20 micrometers on said first copper layer, wherein there is an undercut with an edge of said glue/barrier layer recessed from an edge of said electroplated metal layer, and wherein a first product of resistance of a first section of said coil times capacitance of said first section is at least 100 times smaller than a second product of resistance of a second section of said metal trace times capacitance of said second section, said first section having a same length as said second section;

a metal line on said polymer layer and over said contact point, wherein said metal line is connected to said contact pad through said first and second openings; and

a solder bump is connected to said metal line.

2. The circuit component of claim 1, wherein said second dielectric layer comprises a silicon-based oxide.

3. The circuit component of claim 1, wherein said glue/barrier layer comprises titanium.

4. The circuit component of claim 1, wherein said glue/barrier layer comprises a titanium-tungsten alloy.

5. The circuit component of claim 1, wherein said glue/barrier layer comprises a titanium-containing layer.

6. The circuit component of claim 1, wherein said glue/barrier layer comprises chromium.

7. The circuit component of claim 1, wherein said electroplated metal layer further comprises a nickel-containing layer on said second copper layer.

8. The circuit component of claim 1, wherein said coil comprises an inductor.

9. The circuit component of claim 1, wherein said first product is smaller than said second product by at least 1000 times.

10. The circuit component of claim 1, wherein said first product is smaller than said second product by at least 10,000 times.

11. An integrated circuit structure comprising:

a silicon substrate;

a transistor in and on said silicon substrate;

a first dielectric layer over said silicon substrate;

a metallization structure over said first dielectric layer, wherein said metallization structure comprises a first metal layer, a second metal layer over said first metal layer and a contact point;

a second dielectric layer over said first dielectric layer and between said first and second metal layers, wherein said second dielectric layer has a thickness between 0.1 and 1 micrometer;

a metal trace over said first dielectric layer;

a passivation layer over said metallization structure, over said first and second dielectric layers and over said first and second metal layers, wherein said passivation layer comprises an oxide layer and a nitride layer;

a polymer layer on said passivation layer, wherein said polymer layer has a thickness between 2 and 150 micrometers and greater than that of said passivation layer, wherein an opening in said polymer layer is over said contact point and exposes said contact point;

a coil on said polymer layer, wherein said coil comprises a glue/barrier layer on said polymer layer, a seed layer comprising a first gold layer having a thickness between 0.2 and 1 micrometer on said glue/barrier layer and over said polymer layer, and an electroplated metal layer comprising a second gold layer having a thickness between 3 and 20 micrometers on said first gold layer, wherein there is an undercut with an edge of said glue/barrier layer recessed from an edge of said electroplated metal layer, and wherein a first product of resistance of a first section of said coil times capacitance of said first section is at least 100 times smaller than a second product of resistance of a second section of said metal trace times capacitance of said second section, said first section having a same length as said second section;

a metal line on said polymer layer and over said contact point, wherein said metal line is connected to said contact point through said opening of said polymer layer; and

a wirebonded wire is connected to said metal line.

12. The circuit component of claim 11, wherein said polymer layer comprises polyimide.

13. The circuit component of claim 11, wherein said polymer layer comprises benzocyclobutene (BCB).

14. The circuit component of claim 11, wherein said polymer layer comprises parylene.

15. The circuit component of claim 11, wherein said coil composes an inductor.

16. The circuit component of claim 11, wherein said coil composes a part of a transformer.

17. The circuit component of claim 11, wherein said glue/barrier layer further comprises tungsten.

18. The circuit component of claim 11, wherein said glue/barrier layer has a thickness between 0.05 and 0.5 micrometers.

19. The circuit component of claim 11, wherein said first product is smaller than said second product by at least 1000 times.

20. The circuit component of claim 11, wherein said first product is smaller than said second product by at least 10,000 times.