Touch control apparatus and analog-to-digital converting apparatus and method thereof

• US 20080129571A1
• Filed: 11/28/2007
• Published: 06/05/2008
• Est. Priority Date: 11/30/2006
• Status: Active Grant

• Current Assignee: Realtek Semiconductor Corp.
• Original Assignee: Realtek Semiconductor Corp.
• Inventors: Min, Shawn
• Granted Patent: US 7,541,954 B2
• Time in Patent Office: Days
• US Class Current: 341/155
• CPC Class Codes: H03M 1/0845 of power supply variations, e.g. ripple
• CPC Class Codes: H03M 1/145 the steps being performed sequentially in series-connected stages H03M1/141, H03M1/143, H03M1/16 take precedence
• CPC Class Codes: H03M 1/46 with digital/analogue converter for supplying reference values to converter

Abstract

Disclosed are an analog-to-digital converting apparatus, an analog-to-digital converting method and a touch control apparatus adapted to convert a divided voltage generated according to a power voltage and a ground voltage. The analog-to-digital converting apparatus includes a first sample-and-hold circuit for sampling and holding the divided voltage, a second sample-and-hold circuit for sampling and holding the power voltage, and an analog-to-digital converter coupled to the first and second sample-and-hold circuits. The analog-to-digital converter converts the divided voltage from the first sample-and-hold circuit to a digital value according to the power voltage held by the second sample-and-hold circuit and the ground voltage. The first and second sample-and-hold circuits sample the divided voltage and the power voltage before the analog-to-digital converter converts the divided voltage, and hold the sampled divided voltage and the sampled power voltage at least during conversion of the divided voltage by the analog-to-digital converter.

Claims

1. An analog-to-digital converting method for converting a divided voltage which is generated according to a power voltage and a ground voltage, said analog-to-digital converting method comprising the steps of:

sampling and holding the divided voltage;

sampling and holding the power voltage; and

converting the held divided voltage to a digital value according to the held power voltage and the ground voltage;

wherein sampling of the divided voltage and the power voltage are conducted before the step of converting the held divided voltage, and holding of the sampled divided voltage and the sampled power voltage are conducted at least during the step of converting the held divided voltage.

2. The analog-to-digital converting method as claimed in claim 1, wherein (P.5) bits are generated for each half clock-pulse cycle in the step of converting the held divided voltage, where P is a positive integer.

3. An analog-to-digital converting apparatus for converting a divided voltage which is generated according to a power voltage and a ground voltage, said analog-to-digital apparatus comprising:

a first sample-and-hold circuit for sampling and holding the divided voltage;

a second sample-and-hold circuit for sampling and holding the power voltage; and

an analog-to-digital converter coupled to said first and second sample-and-hold circuits, said analog-to-digital converter converting the divided voltage from said first sample-and-hold circuit to a digital value according to the power voltage held by said second sample-and-hold circuit and the ground voltage;

wherein said first and second sample-and-hold circuits sample the divided voltage and the power voltage before said analog-to-digital converter converts the divided voltage, and hold the sampled divided voltage and the sampled power voltage at least during conversion of the divided voltage by said analog-to-digital converter.

4. The analog-to-digital converting apparatus as claimed in claim 3, wherein said analog-to-digital converter is a successive approximation analog-to-digital converter.

5. The analog-to-digital converting apparatus as claimed in claim 3, wherein said analog-to-digital converter is a cyclic analog-to-digital converter.

6. The analog-to-digital converting apparatus as claimed in claim 5, wherein said analog-to-digital converter generates (P.5) bits for each half clock-pulse cycle, where P is a positive integer.

7. The analog-to-digital converting apparatus as claimed in claim 3, wherein said analog-to-digital converter is a sub-ranging analog-to-digital converter.

8. The analog-to-digital converting apparatus as claimed in claim 3, wherein said analog-to-digital converter is a two-step analog-to-digital converter.

9. The analog-to-digital converting apparatus as claimed in claim 3, wherein said analog-to-digital converter is a pipelined analog-to-digital converter.

10. The analog-to-digital converting apparatus as claimed in claim 9, wherein said analog-to-digital converter includes a plurality of stages, each of which generates (P.5) bits for each half clock-pulse cycle, where P is a positive integer.

11. A touch control apparatus comprising:

a divided voltage source for generating a divided voltage according to a power voltage and a ground voltage; and

an analog-to-digital converting apparatus including;

a first sample-and-hold circuit coupled to said divided voltage source and operable to sample and hold the divided voltage;

a second sample-and-hold circuit for sampling and holding the power voltage; and

an analog-to-digital converter coupled to said first and second sample-and-hold circuits, said analog-to-digital converter converting the divided voltage from said first sample-and-hold circuit to a digital value according to the power voltage held by said second sample-and-hold circuit and the ground voltage;

wherein said first and second sample-and-hold circuits sample the divided voltage and the power voltage before said analog-to-digital converter converts the divided voltage, and hold the sampled divided voltage and the sampled power voltage at least during conversion of the divided voltage by said analog-to-digital converter.

12. The touch control apparatus as claimed in claim 11, wherein said analog-to-digital converter is a successive approximation analog-to-digital converter.

13. The touch control apparatus as claimed in claim 11, wherein said analog-to-digital converter is a cyclic analog-to-digital converter.

14. The touch control apparatus as claimed in claim 13, wherein said analog-to-digital converter generates (P.5) bits for each half clock-pulse cycle, where P is a positive integer.

15. The touch control apparatus as claimed in claim 11, wherein said analog-to-digital converter is a sub-ranging analog-to-digital converter.

16. The touch control apparatus as claimed in claim 11, wherein said analog-to-digital converter is a two-step analog-to-digital converter.

17. The touch control apparatus as claimed in claim 11, wherein said analog-to-digital converter is a pipelined analog-to-digital converter.

18. The touch control apparatus as claimed in claim 17, wherein said analog-to-digital converter includes a plurality of stages, each of which generates (P.5) bits for each half clock-pulse cycle, where P is a positive integer.

19. The touch control apparatus as claimed in claim 11, wherein said divided voltage source is a touch panel.

20. The touch control apparatus as claimed in claim 11, wherein said divided voltage source is an impedance grid.