Method and Structure of a Multi-Level Cell Resistance Random Access Memory with Metal Oxides

• US 20080135824A1
• Filed: 12/07/2006
• Published: 06/12/2008
• Est. Priority Date: 12/07/2006
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Lai, Erh-Kun, Ho, ChiaHua, Hsieh, Kuang Yeu
• Granted Patent: US 7,697,316 B2
• Time in Patent Office: Days
• US Class Current: 257/2
• CPC Class Codes: G11C 11/5664 using organic memory material storage elements
• CPC Class Codes: G11C 11/5678 using amorphous/crystalline phase transition storage elements
• CPC Class Codes: G11C 13/00 Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0014 comprising cells based on organic memory material
• CPC Class Codes: G11C 13/0016 comprising polymers
• CPC Class Codes: H10N 70/028 by conversion of electrode material, e.g. oxidation
• CPC Class Codes: H10N 70/20 Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/8265 on sidewalls of dielectric structures, e.g. mesa-shaped or cup-shaped devices
• CPC Class Codes: H10N 70/8833 Binary metal oxides, e.g. TaOx

Abstract

A method and structure of a bistable resistance random access memory comprise a plurality of programmable resistance random access memory cells where each programmable resistance random access memory cell includes multiple memory members for performing multiple bits for each memory cell The bistable RRAM includes a first resistance random access member connected to a second resistance random access member through interconnect metal liners and metal oxide strips. The first resistance random access member has a first resistance value Ra, which is determined from the thickness of the first resistance random access member based on the deposition of the first resistance random access member. The second resistance random access member has a second resistance value Rb, which is determined from the thickness of the second resistance random access member based on the deposition of the second resistance random access member.

Claims

1. A multi-level cell (MLC) resistance random access memory (RRAM) structure, comprising:

a first programmable resistive memory member having a resistance Ra and a thickness t₁, the resistance Ra correlating with the thickness t₁, the first programmable resistive memory member having a first metal oxide strip on at a first position and a second metal oxide strip at a second position, the first position spaced apart from the second position;

a second programmable resistive memory member having a resistance Rb and a thickness t₂, the resistance Rb correlating with the thickness t₂, the second programmable resistive memory member having a third metal oxide strip at a first position and a fourth metal oxide strip at a second position, the first position spaced apart from the second position;

an insulating member separating the first programmable resistive memory member and the second programmable resistive memory member;

a first interconnect vertically connecting the first metal oxide strip of the first programmable resistive memory member and the third metal oxide strip of the second programmable resistive memory member; and

a second interconnect vertically connecting the second metal oxide strip of the first programmable resistive memory member and the fourth metal oxide strip of the second programmable resistive memory member.

2. The structure of claim 1, wherein the first interconnect comprises a first metal liner interconnect;

and the second interconnect comprises a second metal liner interconnect.

3. The structure of claim 2, wherein the first interconnect comprises a first metal oxide interconnect;

and the second interconnect comprises a second metal oxide interconnect.

8. The method of claim 3, further comprising forming a first interconnect metal liner electrically connecting between the first metal oxide strip of the first programmable resistance random access memory member and the third metal oxide strip of the second programmable resistive memory member.

9. The method of claim 8, further comprising forming a second interconnect metal liner electrically connecting between the second metal oxide strip of the first programmable resistance random access memory member and the fourth metal oxide strip of the second programmable resistive memory member.

10. The method of claim 9, further comprising an incoming electrical current entering the second programmable resistive memory member and splitting into a first current in a first direction and a second current in a second direction of the second programmable resistive memory member, the first direction being opposite of the second direction,

wherein the first current from the first direction flows through the third metal oxide strip, down the first interconnect metal liner, through the first metal oxide strip, across the first programmable resistive memory member,

wherein the second current from the second direction flows through the fourth metal oxide strip, down the second interconnect metal liner, through the second metal oxide strip, across the first programmable resistive memory member, and

wherein the first and second currents merge into an output electrical current.

11. The method of claim 9, further comprising determining a total resistance Rs by summing the resistance Ra and the resistance Rb and dividing the sum by 2, represented mathematically as Rs=(Ra+Rb)/2.

4. A method of forming a multi-level cell (MLC) resistance random access memory (RRAM) structure, comprising:

depositing a first programmable resistive memory member having a thickness t₁, the first programmable resistive memory member having a resistance Ra, the resistance Ra correlating with the thickness t₁ of the first programmable resistance random access memory member;

forming an insulating member over the first programmable resistance random access memory member;

depositing a second programmable resistive memory member having a thickness t₂, the second programmable resistive memory member having a resistance Rb, the resistance Rb correlating with the thickness t₂ of the second programmable resistive memory member; and

oxidizing the first programmable resistive memory member to form a first metal oxide strip at a first position of the first programmable resistive memory member and form a second metal oxide strip at a second position of the first programmable resistance random access memory member, the first metal liner having a vertical thickness MLa and a horizontal thickness MLOXa.

5. The method of claim 4, further comprising oxidizing the second programmable resistive memory member to form a third metal oxide strip at a first position of the second programmable resistive memory member and form a fourth metal oxide strip at a second position of the second programmable resistance random access memory member, the third metal liner having a vertical thickness MLb and a horizontal thickness MLOXb.

6. The method of claim 5, wherein the resistance Ra is a function of the vertical thickness MLa of the first metal oxide strip and the horizontal thickens MLOXa of the first metal oxide strip, represented mathematically as Ra=MLOXa/MLa.

7. The method of claim 6, wherein the resistance Rb is a function of the vertical thickness MLa of the third metal oxide strip and the horizontal thickness MLOXb of the third metal oxide strip, is represented mathematically as Rb=MLOXb/MLb.

12. The method of claim 5, further comprising forming a first interconnect metal oxide electrically connecting between the first metal oxide strip of the first programmable resistance random access memory member and the third metal oxide strip of the second programmable resistive memory member.

13. The method of claim 12, further comprising forming a second interconnect metal oxide electrically connecting between the second metal oxide strip of the first programmable resistive memory member and the fourth metal oxide strip of the second programmable resistive memory member, the first interconnect metal oxide having a resistance Rc.

14. The method of claim 13, further comprising an incoming electrical current entering the second programmable resistive memory member and splitting into a first current in a first direction and a second current in a second direction of the second programmable resistive memory member, the first direction being opposite of the second direction,

wherein the first current from the first direction flows through the third metal oxide strip, down the first interconnect metal oxide, through the first metal oxide strip, across the first programmable resistive memory member,

wherein the second current from the second direction flows through the fourth metal oxide strip, down the second interconnect metal liner, through the second metal oxide strip, across the first programmable resistive memory member, and

wherein the first and second currents merge into an output electrical current.

15. The method of claim 13, further comprising determining a total resistance Rs by summing the resistances, Ra, Rb and Rc, and dividing the sum by 2, represented mathematically as Rs=(Ra+Rb+Rc)/2.

16. The method of claim 4, further comprising forming a cap member over the second programmable resistive memory member.

17. The method of claim 16, further comprising forming a spacer around the first and second metal liners and the cap member.

18. The method of claim 17, further comprising removing the cap member leaving a void;

and forming spacers above the second programmable resistive memory member.

19. The method of claim 18S further comprising depositing a conductive material into the void and between the spacers, the conductive material contacting the second programmable resistive memory member.

20. The method of claim 19, further comprising an electrical current flowing through the conductive material, splitting into a first direction and a second direction of the second programmable resistive memory member, through the first metal liner, the first direction being opposite of the second direction.