Three-dimensional integrated circuits with protection layers

• US 20080142990A1
• Filed: 12/19/2006
• Published: 06/19/2008
• Est. Priority Date: 12/19/2006
• Status: Active Grant

• Current Assignee: Advanced Manufacturing Innovations Incorporated
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yu, Chen-Hua, Tu, Hung-Jung, Chiou, Wen-Chih, Wu, Weng-Jin, Yang, Ku-Feng
• Granted Patent: US 7,812,459 B2
• Time in Patent Office: Days
• US Class Current: 257/777
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05009 Bonding area integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05139 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05157 Cobalt [Co] as principal constituent
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05181 Tantalum [Ta] as principal constituent
• CPC Class Codes: H01L 2224/05184 Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/05186 with a principal constituent of the material being a non metallic, non metalloid inorganic material
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05609 Indium [In] as principal constituent
• CPC Class Codes: H01L 2224/05616 Lead [Pb] as principal constituent
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05684 : Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/13099 : Material
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 27/0688 : Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/013 : Alloys
• CPC Class Codes: H01L 2924/01327 : Intermediate phases, i.e. intermetallics compounds
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: Y10S 148/164 : Three dimensional processing

Abstract

A semiconductor structure includes a first die comprising a first substrate and a first bonding pad over the first substrate, a second die having a first surface and a second surface opposite the first surface, wherein the second die is stacked on the first die and a protection layer having a vertical portion on a sidewall of the second die, and a horizontal portion extending over the first die.

Claims

1. A semiconductor structure comprising:

a first die comprising;

a first substrate; and

a first bonding pad over the first substrate;

a second die having a first surface and a second surface opposite the first surface, wherein the second die is stacked on the first die; and

a protection layer having a vertical portion on a sidewall of the second die, and a horizontal portion extending over the first die.

2. The semiconductor structure of claim 1 further comprising a coating on the horizontal portion of the protection layer and in a region defined by the vertical portion and the horizontal portion of the protection layer.

3. The semiconductor structure of claim 2, wherein a top edge of the vertical portion of the protection layer is substantially level with a top surface of the coating.

4. The semiconductor structure of claim 1, wherein the protection layer comprises a material selected from the group consisting essentially of diamond film, amorphous carbon, silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon oxycarbide, and combinations thereof.

5. The semiconductor structure of claim 1, wherein the protection layer is formed on all sidewalls of the second die, and encircles the second die.

6. The semiconductor structure of claim 1, wherein the protection layer has a thickness of between about 50 Å

and about 2000 Å

.

7. The semiconductor structure of claim 1, wherein the first die further comprises an active device in the first substrate and an interconnect structure over the first substrate, wherein the interconnect structure is connected to the first bonding pad.

8. The semiconductor structure of claim 1, wherein the first die is free from active devices.

9. The semiconductor structure of claim 1 further comprising a third die stacked on the second die, and an additional protection layer on a sidewall of the third die and extending over the second die.

10. The semiconductor structure of claim 1 further comprising a third die stacked on the first die, wherein the protection layer is on a sidewall of the third die and extending over the first die.

11. The semiconductor structure of claim 1, wherein the second die comprises:

a second substrate;

an active device in the second substrate;

an interconnect structure over the second substrate;

a second bonding pad on the first surface and interconnected to the interconnect structure, wherein the second bonding pad is bonded to the first bonding pad of the first die; and

a contact pad on the second surface and electrically connected to the second bonding pad.

12. The semiconductor structure of claim 11 further comprising a through-silicon via in the second substrate and electrically interconnecting the second bonding pad and the contact pad of the second die.

13. A semiconductor structure comprising:

a wafer comprising a first die and a second die, each comprising;

a first substrate; and

a first bonding pad on a top surface of the first substrate;

a third die and a fourth die each having a first surface and a second surface opposite the first surface, wherein the third die is stacked on the first die, and the fourth die is stacked on the second die, and wherein the third and the fourth dies each comprise;

a second substrate;

an active device in the second substrate;

an interconnect structure over the second substrate;

a second bonding pad on the first surface and connected to the interconnect structure, wherein the second bonding pad of the third die is bonded to the first bonding pad of the first die, and wherein the second bonding pad of the fourth die is bonded to the first bonding pad of the second die; and

a contact pad on the second surface and electrically connected to the second bonding pad;

a protection layer in a space between the third and the fourth dies, wherein the protection layer has vertical portions on sidewalls of the third die and the fourth die, and a horizontal portion extending from over the first die to over the second die; and

a coating on the protection layer and filling a remaining space between the third and the fourth dies.

14. The semiconductor structure of claim 13, wherein the protection layer is formed on all sidewalls of the third and the fourth dies and form a continuous layer with the horizontal portion of the protection layer.

15. The semiconductor structure of claim 13, wherein the first die and the second die each comprise active devices.

16. The semiconductor structure of claim 13, wherein the first bonding pad of the first die and the second bonding pad of the third die form a space with neighboring bonding pads, and wherein the space is an air insulation.

17. The semiconductor structure of claim 13, wherein the first bonding pad of the first die and the second bonding pad of the third die form a space with neighboring bonding pads, and wherein the space comprises a gap filling material.

18. A semiconductor structure comprising:

a supporter free from active devices, the supporter comprising;

a first substrate; and

a first bonding pad over the first substrate;

a die having a first surface and a second surface opposite the first surface, wherein the die is stacked on the supporter, the die comprising;

a second substrate;

an active device in the second substrate;

an interconnect structure over the second substrate;

a second bonding pad on the first surface and connected to the interconnect structure, wherein the second bonding pad is bonded to the first bonding pad of the supporter; and

a contact pad on the second surface and electrically connected to the second bonding pad; and

a protection layer having a vertical portion on a sidewall of the second die, and a horizontal portion extending over the supporter.

19. The semiconductor structure of claim 18, wherein the first substrate comprises a dielectric material.

20. The semiconductor structure of claim 18, wherein the supporter further comprises a third bonding pad over the first substrate, and wherein the first and the third bonding pads are electrically connected.

21. A method for forming a semiconductor structure, the method comprising:

providing a wafer comprising a first die and a second die, each comprising;

a first substrate; and

a first bonding pad on a top surface of the wafer;

forming a third die and a fourth die each having a first surface and a second surface opposite the first surface, wherein the third die is stacked on the first die, and the fourth die is stacked on the second die;

forming a protection layer in a space between the third and the fourth dies, wherein the protection layer has vertical portions on sidewalls of the first and the second dies, and a horizontal portion extending from over the first die to over the second die; and

forming a coating on the protection layer and filling a remaining space of the space between the third and the fourth dies.

22. The method of claim 21, wherein the step of forming the third and the fourth dies each comprise:

providing a second substrate;

forming an active device in the second substrate;

forming an interconnect structure over the second substrate;

forming a second bonding pad on the first surface and connected to the interconnect structure, wherein the second bonding pad of the third die is bonded to the first bonding pad of the first die, and wherein the second bonding pad of the fourth die is bonded to the first bonding pad of the second die; and

forming a contact pad on the second surface and electrically connected to the second bonding pad.

23. The method of claim 22 further comprising forming through-silicon vias in the second substrates of the third and fourth dies, wherein the through-silicon vias connect the second bonding pads of the third and fourth dies to the contact pads in respective dies.

24. The method of claim 23, wherein the step of forming through-silicon vias comprises:

forming deep plugs from top surfaces of second substrates of the third and the fourth dies into the second substrates;

after the protection layer and the coating are formed, polishing the second substrates from a side opposite the respective top surfaces of the third and the fourth dies to expose the deep plugs;

removing the deep plugs to form openings; and

filling the openings with a conductive material to form the through-silicon vias.

25. The method of claim 21 further comprising a sawing process to separate the first die and the third die from the second die and the fourth die, wherein the horizontal portion of the protection layer and the coating are sawed through.

26. The method of claim 21, wherein the step of forming the protection layer is performed using a method selected from the group consisting essentially of physical vapor deposition, dipping, plasma enhanced chemical vapor deposition (CVD), low pressure CVD, and atomic layer CVD.

27. The method of claim 21, wherein the step of forming the coating is performed using a method selected from the group consisting essentially of spin coating, stencil, and dipping.

28. The method of claim 21, wherein the horizontal portion and the vertical portions of the protection layer are continuous.

29. The method of claim 21 further comprising forming active devices in the first substrates of the first and the second dies, and forming interconnect structures over the first substrates of the first and the second dies.

30. The method of claim 21, wherein the first and the third dies are stacked by forming a bond between the first bonding pad of the first die and the second bonding pad of the third die, wherein the bond is selected from the group consisting essentially of fusion bonding, diffusion bonding and solder bump.

31. A method for forming a semiconductor structure, the method comprising:

providing a wafer comprising a first die and a second die each comprising;

a first substrate; and

a first bonding pad on a top surface of the first substrate;

forming a third die and a fourth die each having a first surface and a second surface opposite the first surface, wherein the steps of forming each of the third and the fourth dies comprise;

providing a second substrate;

forming an active device in the second substrate;

forming a deep dielectric plug in the second substrate;

forming an interconnect structure physically connected to the deep dielectric plug; and

forming a second bonding pad on the first surface and connected to the interconnect structure;

stacking the first die to the third die with the first bonding pad of the first die bonded to the second bonding pad of the third die;

stacking the second die to the fourth die with the first bonding pad of the second die bonded to the second bonding pad of the fourth die;

forming a protection layer on the third and the fourth dies and in a space between the third and the fourth dies, wherein the protection layer has vertical portions on sidewalls of the third and the fourth dies, and a horizontal portion extending from over the first die to over the second die;

forming a coating on the protection layer and filling a remaining space of the space between the third and the fourth dies;

polishing the coating, the protection layer and the second substrate of the third and the fourth dies to expose the deep dielectric plug;

replacing the deep dielectric plugs of the third and the fourth dies with a conductive material to form through-silicon vias; and

forming contact pads electrically interconnected to the through-silicon vias of the third and fourth dies.

32. The method of claim 31 further comprising a sawing process to separate the first die and the third die from the second die and the fourth die, wherein the horizontal portion and the coating are sawed through.

33. The method of claim 32 further comprising, before the step of sawing, stacking a fifth die on the third die, and forming an additional protection layer on a sidewall of the fifth die.