REPROGRAMMABLE CIRCUIT BOARD WITH ALIGNMENT-INSENSITIVE SUPPORT FOR MULTIPLE COMPONENT CONTACT TYPES

• US 20080143379A1
• Filed: 12/15/2006
• Published: 06/19/2008
• Est. Priority Date: 12/15/2006
• Status: Active Grant

• Current Assignee: Richard Norman
• Original Assignee: Richard Norman
• Inventors: Norman, Richard
• Granted Patent: US 8,124,429 B2
• Time in Patent Office: Days
• US Class Current: 326/39
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 23/5382 Adaptable interconnections, e.g. for engineering changes
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 25/0652 the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/12044 OLED
• CPC Class Codes: H01L 2924/1461 MEMS
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H01L 2924/3025 Electromagnetic shielding
• CPC Class Codes: H05K 1/029 having a programmable lay-out, i.e. adapted for choosing between a few possibilities
• CPC Class Codes: H05K 1/0298 Multilayer circuits
• CPC Class Codes: H05K 1/185 Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit semiconductor chips encapsulated by interconnect and support structures H01L23/5389, H01L24/00
• CPC Class Codes: H05K 2201/10212 Programmable component
• CPC Class Codes: H05K 2201/10674 Flip chip
• CPC Class Codes: Y10T 29/49002 Electrical device making
• CPC Class Codes: Y10T 29/53174 Means to fasten electrical component to wiring board, base, or substrate
• CPC Class Codes: Y10T 29/53183 Multilead component

Abstract

The present invention is directed to a system that programmably interconnects integrated circuit chips and other components at near-intra-chip density. The system'"'"'s contact structure allows it to adapt to components with a wide variety of contact spacings and interconnection requirements, the use of releasable attachment means allows component placement to be modified as needed, the system identifies the contacts and the components to facilitate specifying the inter-component connections, and the system provides signal conditioning and retiming to minimize issues with signal integrity and signal skew.

Claims

1. A substrate on which a plurality of components can be affixed, wherein the substrate can be reversibly electronically programmed to establish signal-conducting interconnections between specified component contacts without having those interconnections pass through reprogrammable interconnection components affixed to said substrate.

2. A substrate as claimed in claim 1, wherein substantially all of at least one surface of said substrate can have components with a contact pitch of one millimeter or larger affixed to said surface, and said substrate is operable to interconnect any combination of sets of signal contacts of affixed components where said contacts are within a region 25 millimeters in radius.

3. A substrate as claimed in claim 2, where said substrate is also operable to interconnect 10% of the signal contacts within any region 25 millimeters in radius to any specified set of signal contacts anywhere on the substrate surface.

4. A substrate as claimed in claim 2, where said substrate comprises at least four layers of embedded packaged Field-Programmable Interconnect Circuit chips.

5. A substrate as claimed in claim 4, where said substrate has an average via density of at least four vias per square millimeter.

6. A substrate as claimed in claim 2, where said substrate comprises one layer of embedded Field-Programmable Interconnect Circuit bare dies.

7. A substrate as claimed in claim 6, where said substrate has an average via density of at least four vias per square millimeter.

8. A substrate as claimed in claim 2, where said substrate comprises a large-area integrated circuit.

9. A substrate as claimed in claim 1, wherein said signal conducting interconnections are programmed through configuring cross points of a network of cross bars.

10. A substrate as claimed in claim 9, wherein said network of cross bars is arranged in a continuous mesh of interconnections of at least two physical dimensions and at least 6 logical dimensions projected onto said at least two physical dimensions.

11. A substrate as claimed in claim 10, wherein said continuous mesh of interconnections comprises at least 14 logical dimensions, and wherein the cross-bar to cross-bar distance spanned by a given connection in each successively higher logical dimension projected onto a given physical dimension is twice the cross-bar to cross-bar distance spanned by the next highest dimension projected onto said given physical dimension.

12. A substrate as claimed in claim 11, wherein some of the cross-bar to cross-bar connections in the highest logical dimension projected onto a given physical dimension are replaced by a connection to a nearest neighbor in that physical dimension.

13. A substrate as claimed in claim 9, wherein said network of cross bars is arranged in a Bene{hacek over (s)} network wherein the central stage of the Bene{hacek over (s)} network has a lower fan-out than the leaf stages of said Bene{hacek over (s)} network.

14. A substrate as claimed in claim 13, wherein at least the three most central stages of the Bene{hacek over (s)} network have fan-out of 2.

15. A substrate as claimed in claim 14, wherein the leaf stages of the Bene{hacek over (s)} network have fan-out at least 8.

16. A substrate as claimed in claim 1, wherein said signal-conducting interconnections are entirely through conductive paths.

17. A substrate as claimed in claim 16 wherein said interconnections are programmed though regions of a material that can be reversibly changed from a high-resistance phase to a low-resistance phase.

18. A substrate as claimed in claim 16 wherein said interconnections are programmed though the reversible movement of conductive members.

19. A substrate as claimed in claim 18 wherein said conductive members are carbon nanotubes.

33. A substrate as claimed in claim 1, wherein the substrate can also be reversibly electronically programmed to establish power-conducting paths to specified component contacts, capable of delivering a current of greater than 100 milliAmperes to each such contact.

34. A substrate as claimed in claim 33, wherein when said substrate site for a component contact is programmed to be a site for a signal contact it is operable to drive a component contact at a signal rate of at least one hundred megabits per second.

35. A substrate as claimed in claim 33, wherein when said substrate site for a component contact is programmed to be a site for a signal contact it is operable to be driven by a component contact at a signal rate of at least one hundred megabits per second.

36. A substrate as claimed in claim 34, wherein when said substrate site for a component contact is programmed to be a site for a signal contact, it is operable to drive a component contact at a signal rate of at least one hundred megabits per second, and it is operable to be driven by a component contact at a signal rate of at least one hundred megabits per second.

37. A substrate as claimed in claim 36, wherein when said substrate site for a component contact is programmed to be a site for a signal contact, it is operable to drive a component contact at a signal rate of at least one gigabit per second, and it is operable to be driven by a component contact at a signal rate of at least one gigabit per second.

38. A substrate as claimed in claim 33, wherein the substrate can also be reversibly electronically programmed to establish power-conducting paths to specified component contacts, capable of delivering a current of greater than 1 Ampere to each such contact.

39. A substrate as claimed in claim 33, wherein the substrate can be reversibly electronically programmed to establish power-conducting paths to a specified component contact from a specified one of multiple power planes that can be at different voltages.

40. A substrate as claimed in claim 33, wherein the substrate can also be reversibly electronically programmed to establish ground paths from specified component contacts, capable of grounding at least 100 milliAmperes from each such contact.

41. A substrate as claimed in claim 1, wherein substantially all of at least one surface of said substrate can have components with a contact pitch as small as one millimeter affixed to said surface, and said substrate is operable to interconnect any combination of sets of signal contacts of affixed components where said contacts are within a region with a radius 25 times said component contact pitch, and wherein said substrate is also operable to interconnect 10% of the signal contacts within any region with a radius 25 times said component contact pitch to any specified set of signal contacts anywhere on the substrate surface, and wherein the substrate can also be reversibly electronically programmed to establish power-conducting paths to specified component contacts of affixed components, capable of delivering a current of greater than 100 milliAmperes to each such power contact, where such power contacts can comprise 10% of all contacts of affixed components, and wherein the substrate can also be reversibly electronically programmed to establish ground paths from specified component contacts, capable of grounding at least 100 milliAmperes from each such ground contact, where such ground contacts can comprise 10% of all contacts of affixed components.

42. A substrate as claimed in claim 41, where any of the component contacts may be signal contacts, power contacts or ground contacts.

43. A substrate as claimed in claim 42, wherein said substrate has power contacts, ground contacts and signal contacts and where any component contact of at least 250 microns in diameter overlaps at least one power contact, at least one ground contact and at least one signal contact.

44. A substrate as claimed in claim 41, wherein substantially all of at least one surface of said substrate can have components where said contact pitch can be as small as 250 microns.

45. A substrate as claimed in claim 44, wherein said signal conducting interconnections are programmed through configuring cross points of a network of cross bars, and each component contact that is a signal contact can drive or be driven by at least one cross point in each of multiple cross bars without passing through an intervening cross bar.

46. A substrate as claimed in claim 41, wherein substantially all of at least one surface of said substrate can have components with any mix of contact pitches of at least one millimeter with contact diameters of at least 250 microns.

47. A substrate as claimed in claim 46, wherein substantially all of at least one surface of said substrate can have components with any mix of contact pitches of at least 250 microns with contact diameters of at least 100 microns.

48. A substrate as claimed in claim 47, wherein substantially all of at least one surface of said substrate can have components with any mix of contact pitches of at least 150 microns with contact diameters of at least 70 microns.

49. A substrate as claimed in claim 41, wherein substantially all of at least one surface of said substrate can have components with up to three pad rings of pad-to-pad and ring-to-ring pitches of at least 50 microns.

50. A substrate as claimed in claim 49, wherein said signal conducting interconnections are programmed through configuring cross points of a network of cross bars, and each component contact that is a signal contact can drive or be driven by at least one cross point in each of multiple cross bars without passing through an intervening cross bar.

51. A substrate as claimed in claim 48, wherein said substrate comprises multiple power planes that can be supplied with power at different voltages, wherein said substrate further comprises a plurality of local power planes with at least one local power plane per square centimeter, wherein a given local power plane can be reversibly electronically programmed to establish one or more power-conducting connections to any of a plurality of power planes, and wherein the substrate can be reversibly electronically programmed to connect a substrate contact to a local power plane.

52. A substrate as claimed in claim 47, wherein multiple substrate contacts can cooperatively drive a component contact whose diameter is at least 100 microns.

70. An apparatus containing a substrate as claimed in claim 1, wherein said apparatus has means for releasably affixing components to the surface of said substrate.

71. An apparatus containing a substrate as claimed in claim 42, wherein said substrate is reprogrammable and said apparatus has means for releasably affixing components to the surface of said substrate.

90. An apparatus as claimed in claim 47, wherein said substrate further comprises means to compare a value received from a component contact to the value that the substrate would receive from that component contact if the component is functioning correctly.

91. An apparatus as claimed in claim 90, wherein said substrate further comprises means to send the results of that comparison to a program external to said substrate.

92. An apparatus as claimed in claim 91, wherein said substrate only sends the result of the comparison if the two values do not match.

93. An apparatus as claimed in claim 92, wherein each contact of said substrate has associated circuitry that can perform a comparison between a value received from a component contact and value that would be received from the component contact if the component is functioning correctly.

94. An apparatus as claimed in claim 47, wherein said substrate further comprises means to compare a value received from a first component contact to a value received from a component contact in the same position on another component, and to send the results of that comparison to a program external to said substrate if the two values do not match.

95. An apparatus as claimed in claim 94, wherein said substrate comprises means to compare a value received from a first component contact to a value received from at least three other component contacts in the same position on other components, and to send the results of that comparison to a program external to said substrate if the first component contact'"'"'s value does not match the value of the majority of the values received from at least three other component contacts.

120. An apparatus containing a substrate as claimed in claim 1, wherein said apparatus further comprises a releasable cover for releaseably affixing components to the surface of said substrate.

20. A substrate on which a plurality of components can be affixed, wherein the substrate can be electronically programmed to establish signal-conducting interconnections between specified component contacts without having those interconnections pass through programmable interconnection components affixed to said substrate, wherein said substrate has signal amplifiers or signal repeaters embedded in it.

21. A substrate as claimed in claim 20, where the maximum signal-conducting path length between a signal contact of an affixed component and the nearest amplifier or repeater on the signal-conducting path within said substrate is at most one centimeter.

22. A substrate as claimed in claim 21, where the maximum signal-conducting path length between a signal contact of an affixed component and the nearest amplifier or repeater on the signal-conducting path within said substrate is at most one millimeter.

23. A substrate as claimed in claim 20, where said substrate also has retiming circuitry embedded in it.

24. A substrate as claimed in claim 23, where the maximum signal-conducting path length between a signal contact of an affixed component and the nearest retiming circuitry on the signal-conducting path within said substrate is at most one centimeter.

25. A substrate as claimed in claim 24, where the maximum signal-conducting path length between a signal contact of an affixed component and the nearest retiming circuitry on the signal-conducting path within said substrate is at most one millimeter.

26. A substrate as claimed in claim 20, wherein said signal conducting interconnections are programmed through a series of cross points in a network of cross bars.

27. A substrate as claimed in claim 26, wherein said network of cross bars is arranged in a continuous mesh of interconnections of at least two physical dimensions and at least 6 logical dimensions projected onto said at least two physical dimensions.

28. A substrate as claimed in claim 27, wherein said continuous mesh of interconnections comprises at least 14 logical dimensions, and wherein the cross-bar to cross-bar distance spanned by a given connection in each successively higher logical dimension projected onto a given physical dimension is twice the cross-bar to cross-bar distance spanned by the next highest dimension projected onto said given physical dimension.

29. A substrate as claimed in claim 28, wherein some of the cross-bar to cross-bar connections in the highest logical dimension projected onto a given physical dimension are replaced by a connection to a nearest neighbor in that physical dimension.

30. A substrate as claimed in claim 26, wherein said network of cross bars is arranged in a Bene{hacek over (s)} network wherein the central stage of the Bene{hacek over (s)} network has a lower fan-out than the leaf stages of said Bene{hacek over (s)} network.

31. A substrate as claimed in claim 30, wherein at least the three most central stages of the Bene{hacek over (s)} network have a fan-out of 2.

32. A substrate as claimed in claim 31, wherein the leaf stages of the Bene{hacek over (s)} network have a fan-out of at least 8.

53. A method for manufacturing a multi-chip module comprising a substrate on which a plurality of components can be affixed, wherein the substrate can be electronically programmed to establish signal-conducting interconnections between specified component contacts, the method comprising determining a position of components affixed to the substrate, and using said position in programming said signal-conducting interconnections between specified component contacts.

54. A method as claimed in claim 53, wherein said determining the position of components comprises processing one or more images of components affixed to the substrate.

55. A method as claimed in claim 53, wherein said determining the position of components comprises detecting the contacts of affixed components.

56. A method as claimed in claim 55, wherein said detecting of the contacts of affixed components uses circuitry embedded in said substrate.

57. A method as claimed in claim 56, wherein said detecting comprises detecting a change in capacitance caused by the proximity of a component contact.

58. A method as claimed in claim 56, wherein said detecting comprises detecting a change in resistance caused by the overlap of a component contact with a plurality of conductive regions on the substrate surface.

59. A method as claimed in claim 58, wherein said detecting comprises determining a degree of overlap of a component contact with a substrate contact.

60. A method as claimed in claim 53, wherein said position of at least one component is compared to a specified position for that component.

61. A method as claimed in claim 60, wherein when the determined position and the specified position of a component differ, the specified position is adjusted until it matches the determined position.

62. A method as claimed in claim 61, wherein the adjustment of said specified position is performed by a program that maintains the specified connectivity of the component to other components as said specified position is adjusted.

63. A method as claimed in claim 61, further comprising communicating the adjusted specified position of said component to a program that is operable to calculate configuration data that would configure said programmable substrate to route the specified interconnections from said component'"'"'s contact to specified other components.

64. A method as claimed in claim 63, further comprising sending said configuration data to said programmable substrate to configure it to interconnect the contacts of said component, in its determined position, to the contacts of specified other components.

65. A method as claimed in claim 55, further comprising identifying the outlines of components from a set of detected component contacts.

66. A method as claimed in claim 65, further comprising identifying components in a components library that match a given identified component outline.

67. A method as claimed in claim 66, further comprising determining whether two contacts of an affixed component have a low-resistance path between them.

68. A method as claimed in claim 67, further comprising determining which sets of contacts of an affixed component have low-resistance paths between them.

69. A method as claimed in claim 68, further comprising identifying components in a components library whose sets of contacts with low resistance paths between them would, if placed on said programmable substrate, match said determined sets of contacts.

72. An apparatus containing a substrate as claimed in claim 64, wherein said substrate is reprogrammable and said apparatus has means for releasably affixing components to the surface of said substrate.

73. An apparatus as claimed in claim 72, wherein said releasably affixing components to said substrate surface is through pressure.

74. An apparatus as claimed in claim 73, wherein said pressure is applied to said components through pressurizing a flexible pouch whose surface presses said components against said substrate surface.

75. An apparatus as claimed in claim 74, wherein said pouch is substantially filled with a substantially incompressible fluid.

76. An apparatus as claimed in claim 75, wherein said fluid has a high thermal conductivity or a high thermal convectivity.

77. An apparatus as claimed in claim 73, wherein said pressure presses said substrate against a substantially flat, mechanically rigid backing.

78. An apparatus as claimed in claim 77, wherein said backing has a thermal coefficient of expansion substantially the same as said substrate.

79. An apparatus as claimed in claim 77, wherein said backing has a high thermal conductivity.

80. An apparatus as claimed in claim 77, wherein said backing can be securely attached to a lid that provides a backstop for a means for applying said pressure to said components.

81. An apparatus as claimed in claim 80, wherein said backing is attached to said lid through a hinge.

82. An apparatus as claimed in claim 80, wherein said backing, said lid, the attachment of said lid to said backing and said pressurizing means can apply any pressure of up to one atmosphere to press said components against said substrate.

83. An apparatus as claimed in claim 82, wherein said backing, said lid, the attachment of said lid to said backing and said pressurizing means can apply any pressure of up to ten atmospheres to press said components against said substrate.

84. An apparatus as claimed in claim 80, wherein said backing is attached to a circuit board that has components on it that are not affixed through pressure, and wherein said circuit board can send signals to and receive signals from said substrate.

85. An apparatus as claimed in claim 77, wherein said backing comprises means to convey signals from the back of said substrate through said backing.

86. An apparatus as claimed in claim 84, wherein said signals are conveyed to and from said substrate though said backing.

87. An apparatus as claimed in claim 86, wherein said signals are conveyed to and from said substrate though a central region of said backing that is within a radius of one centimeter of the center of said substrate.

88. An apparatus as claimed in claim 86, wherein said signals are conveyed to and from said substrate though holes whose diameter is at most one millimeter.

89. An apparatus as claimed in claim 86, wherein said signals are conveyed to and from said substrate though radial slots whose width is at most one millimeter.

96. A substrate on which a plurality of components can be affixed, wherein the substrate has signal-conducting interconnections establish between specified component contacts without having those interconnections pass through other components affixed to said substrate, wherein said substrate has signal amplifiers or signal repeaters embedded in it.

97. A substrate as claimed in claim 96, where the maximum signal-conducting path length between a signal contact of an affixed component and the nearest amplifier or repeater on the signal-conducting path within said substrate is at most one centimeter.

98. A substrate as claimed in claim 97, where the maximum signal-conducting path length between a signal contact of an affixed component and the nearest amplifier or repeater on the signal-conducting path within said substrate is at most one millimeter.

99. A substrate as claimed in claim 96, where said substrate also has retiming circuitry embedded in it.

100. A substrate as claimed in claim 99, where the maximum signal-conducting path length between a signal contact of an affixed component and the nearest retiming circuitry on the signal-conducting path within said substrate is at most one centimeter.

101. A substrate as claimed in claim 100, where the maximum signal-conducting path length between a signal contact of an affixed component and the nearest retiming circuitry on the signal-conducting path within said substrate is at most one millimeter.

102. An alignment-insensitive component connection apparatus comprising a substrate on which at least one component having connection contacts can be affixed, wherein the substrate has an array of micro-contacts dimensioned smaller than said contacts of said component such that at least one of said micro-contacts will be in contact with each one of said component contacts and at least some of said component contacts will be in contact with a plurality of said micro-contacts and none of said micro-contacts will be in contact with two of said component contacts, and switch circuitry for selectively connecting said micro-contacts to component contacts for providing an interconnecting path for said component contacts to other devices.

103. An apparatus as claimed in claim 102, further comprising contact detection circuitry for automatically discovering which ones of said micro-contacts are in electrical contact with said component contacts.

104. An apparatus as claimed in claim 103, wherein said contact detection circuitry is adapted to recognize an identity of said component from at least a layout of said component contacts and output a component identity signal.

105. An apparatus as claimed in claim 102, wherein said apparatus comprises FPIC circuitry connected to said switch circuitry, and said substrate is adapted to support two or more components.

106. An apparatus as claimed in claim 105, wherein said FPIC circuitry is embedded in said substrate.

107. An apparatus as claimed in claim 106, wherein said components are bare die chips, said component contacts are wafer bumps, further comprising an enclosure for securing said components on said substrate with said wafer bumps in electrical contact with said micro-contacts.

108. An apparatus as claimed in claim 107, further comprising a Z-axis conductive film between said components and said substrate.

109. An apparatus as claimed in claim 102, wherein said component is a bare die chip, said component contacts are wafer bumps, said contacts for providing an interconnecting path for said component contacts to other devices comprise an IC package having a conventional arrangement of leads and holding said substrate, further comprising an enclosure for securing said component on said substrate in said package with said wafer bumps in electrical contact with said micro-contacts.

110. A method of prototyping a multi-chip system using a programmable circuit board adapted to receive and programmably interconnect a plurality of components, the method comprising connecting and testing a subset of said components before connecting and testing said subset with more of said components.

111. A method as claimed in claim 110, further comprising generating at least a part of interconnect programming data using a library of component contact data providing component contact function information for a number of components.

112. A method as claimed in claim 111, further comprising automatically recognizing an identity of said component by probing component contacts on said programmable circuit board.

113. A method as claimed in claim 112, wherein said programmable circuit board has alignment-insensitive micro-contacts for receiving contacts of said components, further comprising automatically discovering which ones of said micro-contacts are in electrical contact with said component contacts, and selectively connecting said micro-contacts to contacts for providing an interconnecting path for said component contacts to other devices.

114. A method as claimed in claim 113, wherein said components are manually placed on said substrate, and said components are operational within said multi-chip system as manually positioned.

115. A method as claimed in claim 110, wherein said subset comprises at least two components, and said at least two components are made to function together for their intended purpose as a subsystem before connecting and testing more of said components to make a complete system.

116. A method of manufacturing a multi-chip system using a programmable circuit board having alignment-insensitive micro-contacts for receiving contacts of said components and being adapted to receive and programmably interconnect a plurality of components, the method comprising manually placing said components on said substrate, wherein said components are operational within said multi-chip system as manually positioned.

117. A method of manufacturing a multi-chip system using a programmable circuit board having alignment-insensitive contacts for receiving contacts of said components and being adapted to receive and programmably interconnect a plurality of components, the method comprising automatically discovering which ones of said programmable circuit board contacts are in electrical contact with said component contacts, and selectively connecting said programmable circuit board contacts to an interconnecting path for said component contacts to other devices.

118. A method as claimed in claim 117, further comprising generating at least a part of interconnect programming data using stored component contact data providing component contact function information for said components.

119. A method as claimed in claim 118, further comprising automatically recognizing an identity of said components by probing component contacts on said programmable circuit board, and using said identity to retrieve component contact data for said components.