Microelectronic assemblies having compliancy and methods therefor

• US 20080150121A1
• Filed: 12/20/2006
• Published: 06/26/2008
• Est. Priority Date: 12/20/2006
• Status: Active Grant

• Current Assignee: Tessera, Inc. (Adeia Inc.)
• Original Assignee: Tessera Technologies Hungary Kft. (Adeia Inc.)
• Inventors: Haba, Belgacem, Ovrutsky, David, Oganesian, Vage, Gao, Guilian
• Granted Patent: US 7,749,886 B2
• Time in Patent Office: Days
• US Class Current: 257/692
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/1132 Screen printing, i.e. using a stencil
• CPC Class Codes: H01L 2224/1147 using a lift-off mask
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/12 Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 Silicon [Si]
• CPC Class Codes: H01L 2924/01015 Phosphorus [P]
• CPC Class Codes: H01L 2924/01022 Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01076 : Osmium [Os]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/351 : Thermal stress

Abstract

A method of making a microelectronic assembly includes providing a semiconductor wafer having contacts accessible at a first surface, forming compliant bumps over the first surface and depositing a sacrificial layer over the compliant bumps. The method includes grinding the sacrificial layer and the compliant bumps so as to planarize top surfaces of the compliant bumps, whereby the planarized top surfaces are accessible through said sacrificial layer. The sacrificial layer is removed to expose the compliant bumps and the contacts. A silicone layer is deposited over the compliant bumps and portions of the silicone layer are removed to expose the contacts accessible at the first surface of the semiconductor wafer. Conductive traces are formed having first ends electrically connected with the contacts and second ends overlying the compliant bumps and conductive elements are provided atop the second ends of the traces.

Claims

1. A method of making a microelectronic assembly comprising:

providing a microelectronic element having a first surface and contacts accessible at the first surface;

providing compliant bumps over the first surface of said microelectronic element;

depositing a sacrificial layer over said compliant bumps and the first surface of said microelectronic element, wherein said sacrificial layer covers said compliant bumps;

grinding said sacrificial layer and said compliant bumps so as to planarize top surfaces of said compliant bumps, wherein the planarized top surfaces of said compliant bumps are accessible through said sacrificial layer;

after the grinding step, removing said sacrificial layer; and

forming conductive traces having first ends electrically connected with said contacts and second ends overlying the planarized top surfaces of said compliant bumps.

2. The method as claimed in claim 1, further comprising providing conductive elements in contact with the second ends of said conductive traces.

3. The method as claimed in claim 2, wherein said conductive elements are selected from the group consisting of solder balls, conductive posts and conductive pins.

4. The method as claimed in claim 1, wherein said contacts on said wafer are exposed during the removing said sacrificial layer step.

5. The method as claimed in claim 1, wherein said compliant bumps have sloping sides surrounding the planarized top surfaces, the sloping sides being exposed during the removing said sacrificial layer step.

6. The method as claimed in claim 1, further comprising:

after the removing said sacrificial layer step, depositing a silicone layer over the first surface of said microelectronic element and said compliant bumps;

selectively removing said silicone layer so as to expose said contacts accessible at the first surface of said microelectronic element.

7. The method as claimed in claim 1, wherein said microelectronic element comprises a semiconductor wafer.

8. The method as claimed in claim 1, wherein said microelectronic element comprises at least one memory chip.

9. The method as claimed in claim 1, wherein said microelectronic element comprises at least one DDR chip.

10. The method as claimed in claim 7, further comprising dicing said semiconductor wafer.

11. The method as claimed in claim 1, further comprising providing conductive posts in contact with the second ends of said conductive traces, said conductive posts overlying said compliant bumps and projecting away from the first surface of said microelectronic element, wherein said conductive posts are electrically interconnected with said contacts of said microelectronic element.

12. The method as claimed in claim 11, wherein said conductive posts have tips that define the highest point on said microelectronic assembly.

13. The method as claimed in claim 1, wherein the providing compliant bumps step comprises:

depositing a layer of a material having a low modulus of elasticity;

selectively removing portions of said layer of low modulus material for forming said compliant bumps.

14. The method as claimed in claim 1, wherein the providing compliant bumps step comprises:

screen printing bumps of a curable material onto the first surface of said microelectronic element;

curing said curable material to form said compliant bumps.

15. The method as claimed in claim 1, wherein said sacrificial layer comprises a photoimageable layer.

16. The method as claimed in claim 15, wherein said sacrificial layer comprises silicone.

17. The method as claimed in claim 1, wherein said compliant bumps comprise a material selected from the group consisting of silicones, flexibilized epoxies, polyimides, thermosetting polymers, fluoropolymers and thermoplastic polymers.

18. The method as claimed in claim 1, wherein after the grinding step said compliant bumps have top surfaces that are substantially flat.

19. The method as claimed in claim 1, wherein said conductive traces comprise material selected from the group consisting of copper, gold, nickel and alloys, combinations and composites thereof.

20. The method as claimed in claim 1, wherein each said conductive post has a base adjacent one of said compliant bumps and a tip remote from the one of said compliant bumps.

21. The method as claimed in claim 19 wherein each said conductive post has a height of about 50-300 micrometers.

22. The method as claimed in claim 19, wherein at least one of said conductive posts has a frustoconical shape with the base having a diameter of about 100-600 micrometers and the tip having a diameter of about 40-200 micrometers.

23. The method as claimed in claim 1, wherein said conductive elements comprise materials selected from the group consisting of copper, copper alloys, gold and combinations thereof.

24. A method of making a microelectronic assembly comprising:

providing a microelectronic element having a first surface and contacts accessible at the first surface;

providing dielectric bumps over the first surface of said microelectronic element;

depositing a sacrificial layer over said dielectric bumps;

grinding said sacrificial layer and said dielectric bumps so as to planarize top surfaces of said dielectric bumps, wherein the planarized top surfaces are accessible through said sacrificial layer;

after the grinding step, removing said sacrificial layer so as to expose said dielectric bumps and said contacts;

depositing a dielectric layer over the first surface of said microelectronic element and said dielectric bumps;

selectively removing said dielectric layer so as to expose said contacts accessible at the first surface of said microelectronic element;

forming conductive traces having first ends electrically connected with said contacts and second ends overlying the planarized top surfaces of said dielectric bumps; and

providing conductive elements in contact with the second ends of said conductive traces.

25. The method as claimed in claim 24, wherein said conductive elements are selected from the group consisting of solder balls, conductive posts and conductive pins.

26. The method as claimed in claim 25, wherein said microelectronic element comprises a semiconductor wafer including one or more memory chips.

27. The method as claimed in claim 24, wherein said sacrificial layer is photoimageable and comprises silicone.

28. The method as claimed in claim 24, wherein said dielectric bumps comprise a material selected from the group consisting of silicones, flexibilized epoxies, polyimides, thermosetting polymers, fluoropolymers and thermoplastic polymers.

29. The method as claimed in claim 24, wherein after the grinding step said dielectric bumps have top surfaces that are substantially flat.

30. The method as claimed in claim 24 wherein said conductive traces comprise material selected from the group consisting of copper, gold, nickel and alloys, combinations and composites thereof.

31. The method as claimed in claim 24, wherein said conductive elements comprise conductive posts disposed atop said dielectric bumps, wherein each said conductive post has a height of about 50-300 micrometers.

32. The method as claimed in claim 24, wherein said conductive elements comprise materials selected from the group consisting of copper, copper alloys, gold and combinations thereof.

33. A method of making a microelectronic assembly comprising:

providing a semiconductor wafer having a first surface and contacts accessible at the first surface;

forming compliant bumps over the first surface of said semiconductor wafer;

depositing a sacrificial layer over said compliant bumps;

grinding said sacrificial layer and said compliant bumps so as to planarize top surfaces of said compliant bumps, wherein the planarized top surfaces of said compliant bumps are accessible through said sacrificial layer;

after the grinding step, removing said sacrificial layer so as to expose said compliant bumps and said contacts;

depositing a silicone layer over the first surface of said microelectronic element and said compliant bumps;

selectively removing said silicone layer so as to expose said contacts accessible at the first surface of said semiconductor wafer;

forming conductive traces having first ends electrically connected with said contacts and second ends overlying the planarized top surfaces of said compliant bumps; and

providing conductive elements in contact with the second ends of said conductive traces.

34. The method as claimed in claim 33, wherein said conductive elements comprise conductive posts.

35. The method as claimed in claim 34, further comprising plating said conductive posts atop the second ends of said conductive traces and overlying said compliant bumps.

36. The method as claimed in claim 33, further comprising dicing said semiconductor wafer to provide a plurality of individual chip packages.

37. A microelectronic assembly comprising:

a semiconductor wafer having a first surface and contacts accessible at the first surface;

compliant bumps overlying the first surface of said semiconductor wafer, each said compliant bump having a planar top surface;

a silicone layer overlying the first surface of said semiconductor wafer and said compliant bumps, wherein the planar top surfaces of said compliant bumps and said contacts are accessible through said silicone layer;

conductive traces having first ends electrically connected with said contacts and second ends overlying the planarized top surfaces of said compliant bumps; and

conductive elements in contact with the second ends of said conductive traces.

38. The assembly as claimed in claim 37, wherein said conductive elements are selected from the group consisting of solder balls, conductive posts and conductive pins.

39. The assembly as claimed in claim 37, wherein said semiconductor wafer comprises one or more memory chips.

40. The assembly as claimed in claim 39, wherein said wafer comprises one or more double-data-rate (DDR) chips.