Inverter circuit with switch circuit having two transistors operating alternatively

• US 20080151587A1
• Filed: 12/21/2007
• Published: 06/26/2008
• Est. Priority Date: 12/22/2006
• Status: Active Grant

• Current Assignee: InnoLux Corporation
• Original Assignee: Innocom Technology Limited, Innolux Display Corporation (InnoLux Corporation)
• Inventors: Lu, Jian-Hui, Zhou, Tong
• Granted Patent: US 7,787,273 B2
• Time in Patent Office: Days
• US Class Current: 363/133
• CPC Class Codes: H02M 1/009 having two or more independently controlled outputs for DC-DC converter with intermediate AC H02M3/33561
• CPC Class Codes: H02M 7/5381 Parallel type

Abstract

An exemplary inverter circuit (2) includes a first switch circuit (22) including a first transistor (221) and a second transistor (222); a second switch circuit (23) including a third transistor (231) and a fourth transistor (232); and a pulse width modulation circuit (21) including a first output terminal (211) and a second output terminal (212). A gate electrode of the first transistor is connected to the first output port. A gate electrode of the second transistor is connected to the second output port. A gate electrode of the third transistor is connected to the first output port. A gate electrode of the fourth transistor is connected to the second output port. A drain electrode of the third transistor is connected to a drain electrode of the first transistor, and a drain electrode of the fourth transistor is connected to a drain electrode of the second transistor.

Claims

1. An inverter circuit, comprising:

a direct current input terminal connected to a direct current power supply;

a first transformer comprising a first primary winding, a second primary winding, and a secondary winding configured for outputting an alternating current voltage;

a second transformer comprising a first primary winding, a second primary winding, and a secondary winding configured for outputting an alternating current voltage;

a pulse width modulation circuit comprising a first output terminal and a second output terminal;

a first switch circuit comprising a first transistor and a second transistor; and

a second switch circuit comprising a third transistor and a fourth transistor;

wherein a gate electrode of the first transistor is connected to the first output port, a source electrode of the first transistor is connected to ground;

a gate electrode of the second transistor is connected to the second output port, a source electrode of the second transistor is connected to ground;

a gate electrode of the third transistor is connected to the first output port, a source electrode of the third transistor is connected to ground;

a gate electrode of the fourth transistor is connected to the second output port, a source electrode of the fourth transistor is connected to ground;

a drain electrode of the third transistor is connected to a drain electrode of the first transistor, a drain electrode of the fourth transistor is connected to a drain electrode of the second transistor;

the first primary winding and the second primary winding share a first tap, the first tap is connected to the direct current input terminal, the other tap of the first primary winding is connected to the drain electrode of the first transistor, the other tap of the second primary winding is connected to the drain electrode of the second transistor; and

the third primary winding and the fourth primary winding share a second tap, the second tap is connected to the direct current input terminal, the other tap of the third primary winding is connected to the drain electrode of the first transistor, the other tap of the third primary winding is connected to the drain electrode of the second transistor.

2. The inverter circuit as claimed in claim 1, further comprising a first filter circuit and a second filter circuit, wherein the first filter circuit is connected between the first tap and ground, the second filter circuit is connected between the second tap and ground.

3. The inverter circuit as claimed in claim 2, wherein each filter circuit comprises a resistor and a capacitor connected in series.

4. The inverter circuit as claimed in claim 3, wherein the direct current input terminal is connected to ground via a capacitor.

5. The inverter circuit as claimed in claim 4, wherein the drain electrode of the fourth transistor is connected to ground via a capacitor.

6. The inverter circuit as claimed in claim 1, wherein the first switch circuit is installed in a first chip and the second switch circuit is installed in a second chip.

7. The inverter circuit as claimed in claim 1, wherein the first transistor, the second transistor, the third transistor, and the fourth transistor are N-channel metal-oxide-semiconductor field-effect transistors.

8. An inverter circuit, comprising:

a direct current input terminal connected to a direct current power supply;

a first transformer comprising a first primary winding, a second primary winding, and a secondary winding configured for outputting an alternating current voltage;

a second transformer comprising a first primary winding, a second primary winding, and a secondary winding configured for outputting an alternating current voltage;

a first switch circuit comprising a first transistor and a second transistor;

a second switch circuit comprising a third transistor and a fourth transistor; and

a pulse width modulation circuit configured for outputting a first square wave signal to turn on or turn off the first transistor and the third transistor and a second square wave signal to turn on or turn off the second transistor and the fourth transistor;

wherein phases of the first square wave signal and the second square wave signal are opposite;

when the first square wave signal is a high level and the second square wave signal is a low level, a first current path is formed sequentially through the direct current input terminal, a first parallel circuit formed by the first primary winding and the third primary winding, a second parallel circuit formed by the first transistor and the third transistor, and ground;

when the first square wave signal is a low level and the second square wave signal is a high level, a second current path is formed sequentially through the direct current input terminal, a third parallel circuit formed by the second primary winding and the fourth primary winding, a fourth parallel circuit formed by the second transistor and the fourth transistor, and ground.

9. The inverter circuit as claimed in claim 8, wherein the first primary winding and the second primary winding share a first tap, the first tap is connected to the direct current input terminal, the other tap of the first primary winding is connected to a drain electrode of the first transistor, the other tap of the second primary winding is connected to a drain electrode of the second transistor, the third primary winding and the fourth primary winding share a second tap, the second tap is connected to the direct current input terminal, the other tap of the third primary winding is connected to the drain electrode of the first transistor, the other tap of the third primary winding is connected to the drain electrode of the second transistor.

10. The inverter circuit as claimed in claim 9, wherein a source electrode of the first transistor is connected to ground, a source electrode of the second transistor is connected to ground, a source electrode of the third transistor is connected to ground, a source electrode of the fourth transistor is connected to ground, a drain electrode of the third transistor is connected to the drain electrode of the first transistor, a drain electrode of the fourth transistor is connected to the drain electrode of the second transistor.

11. The inverter circuit as claimed in claim 10, wherein the pulse width modulation circuit comprises a first output terminal and a second output terminal, a gate electrode of the first transistor is connected to the first output port, a gate electrode of the second transistor is connected to the second output port, a gate electrode of the third transistor is connected to the first output port, a gate electrode of the fourth transistor is connected to the second output port.

12. The inverter circuit as claimed in claim 11, further comprising a first filter circuit and a second filter circuit, wherein the first filter circuit is connected between the first tap and ground, the second filter circuit is connected between the second tap and ground.

13. The inverter circuit as claimed in claim 12, wherein each filter circuit comprises a resistor and a capacitor connected in series.

14. The inverter circuit as claimed in claim 13, wherein the direct current input terminal is connected to ground via a capacitor.

15. The inverter circuit as claimed in claim 14, wherein the drain electrode of the fourth transistor is connected to ground via a capacitor.

16. The inverter circuit as claimed in claim 8, wherein the first switch circuit is installed in a first chip and the second switch circuit is installed in a second chip.

17. The inverter circuit as claimed in claim 8, wherein first transistor, the second transistor, the third transistor, and the fourth transistor are N-channel metal-oxide-semiconductor field-effect transistors.