Interleaved memory program and verify method, device and system

• US 20080151637A1
• Filed: 12/20/2006
• Published: 06/26/2008
• Est. Priority Date: 12/20/2006
• Status: Active Grant

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Doyle, Daniel H.
• Granted Patent: US 7,539,062 B2
• Time in Patent Office: Days
• US Class Current: 365/185.22
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/3454 Arrangements for verifying correct programming or for detecting overprogrammed cells
• CPC Class Codes: G11C 16/3481 Circuits or methods to verify correct programming of nonvolatile memory cells whilst programming is in progress, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate programming
• CPC Class Codes: G11C 2216/22 Nonvolatile memory in which reading can be carried out from one memory bank or array whilst a word or sector in another bank or array is being erased or programmed simultaneously
• CPC Class Codes: G11C 7/1042 using interleaving techniques, i.e. read-write of one part of the memory while preparing another part

Abstract

An interleaved memory programming and verification method, device and system includes a memory array includes first and second memory banks of memory cells. The memory device further includes a controller configured to concurrently program a first data into the first memory bank and a second data into the second memory bank using iterative programming and verification operations in each of the first and second memory banks with the programming and verification operations in the second memory bank being offset from the programming and verification operations in the first memory bank.

Claims

1. A memory device, comprising:

a memory array including a first memory bank and a second memory bank of memory cells; and

a controller configured to program a first and second data into the memory array by concurrently programming the first data into one of the first and second memory banks and verifying the second data in the other one of the first and second memory banks.

2. The memory device of claim 1, further comprising an I/O buffer configured to receive the first and second data for programming into the respective first and second memory banks.

3. The memory device of claim 2, further comprising a shared data cache configured to cache the first data from the I/O buffer until the first memory bank is readied to program the first data therein and further configured to subsequently cache the second data from the I/O buffer until the second memory bank is readied to program the second data therein.

4. The memory device of claim 2, further comprising:

a first data cache configured to cache the first data from the I/O buffer until the first memory bank is readied to program the first data therein; and

a second data cache configured to cache the second data from the I/O buffer until the second memory bank is readied to program the second data therein,

5. The memory device of claim 1, further comprising first and second sense amplifiers respectively operatively coupled with the first and second memory banks, the first and second sense amplifiers each including a latch to respectively store the first and second data during iterative programming and verification operations in the first and second memory banks.

6. The memory device of claim 5, further comprising first and second comparators configured to respectively verify the first and second data with first and second sensed data sensed by the first and second sense amplifiers during the verification operation.

7. The memory device of claim 6, wherein the controller is further configured to repeatedly perform a subsequent programming and verification operation on at least one of the first and second memory banks when the respective first and second data do not match the first and second sensed data.

8. The memory device of claim 5, wherein the first and second sense amplifiers are further configured to latch the first and second data directly from an external interface of the memory device.

9. The memory device of claim 5, further comprising a shared data cache and wherein the first and second sense amplifiers are further configured to latch the first and second data from the shared data cache.

10. The memory device of claim 5, further comprising first and second data caches and wherein the first and second sense amplifiers are further configured to respectively latch the first and second data from the first and second data caches.

11. A non-volatile memory device, comprising:

first and second memory banks; and

a controller configured to concurrently program a first data into the first memory bank and a second data into the second memory bank using iterative programming and verification operations in each of the first and second memory banks with the programming and verification operations in the second memory bank being offset from the programming and verification operations in the first memory bank.

12. The non-volatile memory device of claim 11, further comprising a shared data cache configured to cache the first data received from an external interface of the non-volatile memory device until commencement of the programming and verification operations of the first memory bank and further configured to cache the second data received from an external interface of the non-volatile memory device until commencement of the programming and verification operations of the second memory bank.

13. The non-volatile memory device of claim 11, further comprising a first data cache configured to cache the first data received from an external interface of the non-volatile memory device until commencement of the programming and verification operations of the first memory bank and a second data cache configured to cache the second data received from an external interface of the non-volatile memory device until commencement of the programming and verification operations of the second memory bank.

14. The non-volatile memory device of claim 11, wherein the controller is further configured to terminate the iterative programming and verification operations of one of the first and second memory banks when a respective one of a sensed first and second sensed data respectively match a respective one of the first and second data.

15. A memory system, comprising:

a memory controller; and

a memory device coupled to the memory controller, the memory device including first and second memory banks and a controller configured to concurrently program a first data into the first memory bank and a second data into the second memory bank using iterative programming and verification operations in each of the first and second memory banks with the programming and verification operations in the second memory bank being offset from the programming and verification operations in the first memory bank.

16. An electronic system, comprising:

at least one input/output device; and

a memory device including a first and second memory bank and a controller configured to concurrently program a first data into the first memory bank and a second data into the second memory bank using iterative programming and verification operations in each of the first and second memory banks with the programming and verification operations in the second memory bank being offset from the programming and verification operations in the first memory bank.

17. A method of programming a non-volatile memory array, comprising:

iteratively programming and verifying a first data in a first memory bank of the non-volatile memory array; and

concurrently iteratively programming and verifying a second data in a second memory bank of the non-volatile memory array offset from the iteratively programming and verifying in the first memory bank.

18. The method of claim 17, further comprising caching the first and second data in a shared cache configured to cache the first data until commencement of the iteratively programming and verifying of the first data and further configured to cache the second data until commencement of the concurrently iteratively programming and verifying of the second data.

19. The method of claim 17, further comprising:

caching in a first data cache configured to cache the first data until commencement of the iteratively programming and verifying of the first data; and

caching in a second data cache configured to cache the second data until commencement of the concurrently iteratively programming and verifying of the second data.

20. The method of claim 17, further comprising terminating iteratively programming and verifying one of the first and second data when a respective one of a sensed first and second sensed data respectively matches a respective one of the first and second data.

21. The method of claim 17, wherein the verifying a first and second data comprises sensing a first and second sensed data and respectively comparing for a match the first and second sensed data with the first and second data.

22. A method of writing data to a memory array, comprising:

storing a first data in first sense amplifiers of a first memory bank of the memory array;

storing a second data in second sense amplifiers of a second memory bank of the memory array; and

concurrently alternating programming and verifying the first data in the first memory bank and the second data in the second memory bank.

23. The method of claim 22, further comprising caching the first data in a shared cache configured to cache the first data until commencement of the concurrently alternating programming and verifying the first data in the first memory bank and caching the second data until commencement of the concurrently alternating programming and verifying the second data in the second memory bank.

24. The method of claim 22, further comprising:

caching in a first data cache configured to cache the first data until commencement of the concurrently alternating programming and verifying of the first data in the first memory bank; and

caching in a second data cache configured to cache the second data until commencement of the concurrently alternating programming and verifying of the second data in the second memory bank.

25. The method of claim 22, further comprising terminating concurrently alternating programming and verifying one of the first and second data when one of a sensed first and second sensed data respectively matches a respective one of the first and second data.

26. The method of claim. 22, wherein the verifying a first and second data comprises respectively sensing first and second sensed data and respectively comparing for a match the first and second sensed data with the first and second data.