Semiconductor device

• US 20080151660A1
• Filed: 12/14/2007
• Published: 06/26/2008
• Est. Priority Date: 12/26/2006
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Kurokawa, Yoshiyuki, Inoue, Takayuki
• Granted Patent: US 7,773,436 B2
• Time in Patent Office: Days
• US Class Current: 365/200
• CPC Class Codes: G11C 29/70 Masking faults in memories by using spares or by reconfiguring
• CPC Class Codes: G11C 5/141 Battery and back-up supplies
• CPC Class Codes: G11C 5/142 Contactless power supplies, e.g. RF, induction, or IR

Abstract

An object is to provide a semiconductor device having a memory which can efficiently improve a yield by employing a structure which facilitates the use of a spare memory cell. The semiconductor device includes a memory cell array having a memory cell and a spare memory cell, a decoder connected to the memory cell and the spare memory cell, a data holding circuit connected to the decoder, and a battery which supplies electric power to the data holding circuit. The spare memory cell operates in accordance with an output from the data holding circuit.

Claims

1. A semiconductor device comprising:

a memory cell array comprising a memory cell and a spare memory cell;

a decoder connected to the memory cell and the spare memory cell;

a data holding circuit connected to the decoder; and

a battery configured to supply electric power to the data holding circuit,

wherein the spare memory cell is configured to operate in accordance with an output from the data holding circuit.

2. The semiconductor device according to claim 1, wherein the battery comprises an antenna circuit and a power storage circuit and is configured to charge the power storage circuit with electric power received wirelessly from an outside through the antenna circuit.

3. The semiconductor device according to claim 2, wherein the power storage circuit comprises one of a lithium battery, nickel metal hydride battery, and an electric double-layer capacitor.

4. The semiconductor device according to claim 1, wherein each of the memory cell and the spare memory cell is an SRAM.

5. A semiconductor device comprising:

a memory cell array comprises a memory cell and a spare memory cell;

a decoder connected to the memory cell through a word line and connected to the spare memory cell through a spare memory word line;

a read/write circuit connected to the memory cell and the spare memory cell through a bit line;

a data holding circuit connected to the decoder, and

a battery configured to supply electric power to the data holding circuit,

wherein the spare memory cell is configured to operate in accordance with an output from the data holding circuit.

6. The semiconductor device according to claim 5, wherein the battery comprises an antenna circuit and a power storage circuit and is configured to charge the power storage circuit with electric power received wirelessly from an outside through the antenna circuit.

7. The semiconductor device according to claim 6, wherein the power storage circuit comprises one of a lithium battery, nickel metal hydride battery, and an electric double-layer capacitor.

8. The semiconductor device according to claim 5, wherein each of the memory cell and the spare memory cell is an SRAM.

9. A semiconductor device comprising:

a memory cell array comprising;

a first memory cell connected to a first word line;

a second memory cell connected to a second word line; and

a spare memory cell connected to a spare memory word line,

a driver circuit operationally connected to the memory cell array; and

a data holding circuit capable of storing information and outputting a signal based on the information, wherein the information relates to a necessity of using the spare memory cell depending upon whether at least one of the first memory cell and the second memory cell is defective or not,

wherein the driver circuit is configured to drive the spare memory cell in response to the signal from the data holding circuit.

10. The semiconductor device according to claim 9, wherein the driver circuit is connected to the data holding circuit through a data signal line, an address signal line, the first word line, the second word line, and the spare memory word line.

11. The semiconductor device according to claim 9, wherein the data holding circuit comprises an analog switch and a latch, and the analog switch is connected to a control signal line, an analog switch switching signal line, an inverted analog switch switching signal line.

12. The semiconductor device according to claim 9, further comprising a battery configured to supply electric power to the data holding circuit.

13. The semiconductor device according to claim 12, wherein the battery comprises an antenna circuit and a power storage circuit and is configured to charge the power storage circuit with electric power received wirelessly from an outside through the antenna circuit.

14. The semiconductor device according to claim 13, wherein the power storage circuit comprises one of a lithium battery, nickel metal hydride battery, and an electric double-layer capacitor.

15. The semiconductor device according to claim 12, wherein the battery comprises a current-collecting thin film, a negative electrode active material layer, a solid electrolyte layer, a positive electrode active material layer, and a current-collecting thin film stacked sequentially.

16. The semiconductor device according to claim 9, wherein each of the memory cell and the spare memory cell is an SRAM.

17. The semiconductor device according to claim 10, wherein the data signal line is configured to transmit the signal based on the information from the data holding circuit to the driver circuit.

18. The semiconductor device according to claim 11, wherein the data holding circuit is configured to receive the information to be stored from the control signal line.

19. The semiconductor device according to claim 10, wherein the driver circuit decodes address information transmitted through the address signal line, and decodes the signal output from the data holding circuit transmitted through the data signal line.

20. A method of driving a semiconductor device comprising:

a memory cell array comprising a memory cell and a spare memory cell;

a decoder connected to the memory cell and the spare memory cell;

a data holding circuit connected to the decoder; and

a battery configured to supply electric power to the data holding circuit,

wherein an information that the spare memory cell is to be used is written to the data holding circuit when the memory cell is defective, and

wherein the spare memory cell is configured to operate in accordance with an output from the data holding circuit.

21. The semiconductor device according to claim 20, wherein the battery comprises an antenna circuit and a power storage circuit and is configured to charge the power storage circuit with electric power received wirelessly from an outside through the antenna circuit.

22. The semiconductor device according to claim 21, wherein the power storage circuit comprises one of a lithium battery, nickel metal hydride battery, and an electric double-layer capacitor.

23. The semiconductor device according to claim 20, wherein each of the memory cell and the spare memory cell is an SRAM.

24. The method of driving a semiconductor device according to claim 20, wherein the decoder is operationally connected to an address signal line, a data signal line connected to the data holding circuit, a first word line connected to the first memory cell, a second word line connected to the second memory cell, and a spare memory word line connected to the spare memory cell.