Block-based data striping to flash memory

• US 20080155160A1
• Filed: 01/25/2007
• Published: 06/26/2008
• Est. Priority Date: 12/20/2006
• Status: Active Grant

• Current Assignee: SMART Modular Technologies Incorporated (Smart Global Holdings Incorporated)
• Original Assignee: Smart Module Technologies, Inc.
• Inventors: McDaniel, Ryan Cartland
• Granted Patent: US 7,660,911 B2
• Time in Patent Office: Days
• US Class Current: 710/306
• CPC Class Codes: G06F 13/4027 using bus bridges G06F13/4022 takes precedence

Abstract

In various embodiments, options for data striping to FLASH memory are provided. In one embodiment, an apparatus is provided. The apparatus includes an SATA to ATA bridge, an ATA to USB bridge coupled to the SATA to ATA bridge, and a USB interface coupled to the ATA to USB bridge. The apparatus also includes a first FLASH memory controller coupled to the USB interface. The apparatus further includes a first FLASH memory module coupled to the first FLASH memory controller. The apparatus also includes a second FLASH memory controller coupled to the USB interface and a second FLASH memory module coupled to the second FLASH memory controller. A method for block striping data to or from a plurality of read or write channels.

Claims

1. An apparatus, comprising:

an SATA to ATA bridge;

an ATA to USB bridge coupled to the SATA to ATA bridge;

a USB interface coupled to the ATA to USB bridge;

a block data striper coupled to the ATA to USB bridge and the USB interface;

a first FLASH memory controller coupled to the USB interface;

a first FLASH memory module coupled to the first FLASH memory controller;

a second FLASH memory controller coupled to the USB interface; and

a second FLASH memory module coupled to the second FLASH memory controller.

2. The apparatus of claim 1, further comprising:

a buffer coupled to the ATA to USB bridge.

3. The apparatus of claim 2, further comprising:

a third FLASH memory controller coupled to the USB interface; and

a third FLASH memory module coupled to the third FLASH memory controller.

4. The apparatus of claim 3, further comprising:

a fourth FLASH memory controller coupled to the USB interface; and

a fourth FLASH memory module coupled to the fourth FLASH memory controller.

5. The apparatus of claim 4, further comprising:

a fifth FLASH memory module coupled to the first FLASH memory controller;

a sixth FLASH memory module coupled to the second FLASH memory controller;

a seventh FLASH memory module coupled to the third FLASH memory controller; and

an eighth FLASH memory module coupled to the fourth FLASH memory controller.

6. The apparatus of claim 5, wherein:

the ATA to USB interface, the block data striper, and the buffer are implemented as an FPGA.

7. The apparatus of claim 6, further comprising:

a drive identifier EEPROM coupled to the FPGA.

8. The apparatus of claim 6, further comprising:

a connector coupled to the FPGA.

9. The apparatus of claim 8, further comprising:

a separate daughter board, the daughter board including;

a mating connector coupled to the connector;

a fifth FLASH memory controller coupled to the mating connector;

a ninth FLASH memory module coupled to the fifth FLASH memory controller;

a sixth FLASH memory controller coupled to the mating connector; and

a tenth FLASH memory module coupled to the sixth FLASH memory controller.

10. The apparatus of claim 9, wherein the daughter board further includes:

an eleventh FLASH memory module coupled to the fifth FLASH memory controller;

a twelfth FLASH memory module coupled to the sixth FLASH memory controller;

a seventh FLASH memory controller coupled to the mating connector;

a thirteenth FLASH memory module coupled to the seventh FLASH memory controller;

a fourteenth FLASH memory module coupled to the seventh FLASH memory controller;

an eighth FLASH memory controller coupled to the mating connector;

a fifteenth FLASH memory module coupled to the eighth FLASH memory controller; and

a sixteenth FLASH memory module coupled to the eighth FLASH memory controller.

11. The apparatus of claim 10, wherein the daughter board further includes:

a USB interface coupled to the mating connector, the USB interface coupled between the mating connector and the fifth FLASH memory controller, the sixth FLASH memory controller, the seventh FLASH memory controller and the eighth FLASH memory controller.

12. The apparatus of claim 6, further comprising:

means for identifying the apparatus electronically.

13. A method, comprising:

receiving data via an SATA bus;

translating the data into ATA format;

separating the data into blocks;

packaging the data in blocks for USB transmission;

transferring the data in blocks in USB format; and

storing the data in blocks in a set of FLASH memory modules.

14. The method of claim 13, further comprising:

buffering the data.

15. The method of claim 14, further comprising:

receiving a data request in SATA format;

translating the request into ATA format;

translating the request into USB format;

relaying the request to the set of FLASH memory modules based on locations of blocks of data of the request;

retrieving corresponding data from the set of FLASH memory modules;

transferring the corresponding data in USB format;

transforming the corresponding data to ATA format;

transforming the corresponding data to SATA format; and

transferring the corresponding data as a response to the request.

16. The method of claim 15, further comprising:

providing a drive identification responsive to a request.

17. A method, comprising:

receiving a data request in SATA format;

translating the request into USB format;

relaying the request to memory based on block locations of the request;

retrieving corresponding data from memory;

transferring the corresponding data in USB format;

transforming the corresponding data to SATA format; and

transferring the corresponding data as a response to the request.

18. The method of claim 17, further comprising:

translating the request into ATA format; and

transforming the corresponding data to ATA format.

19. The method of claim 18, further comprising:

buffering the data request.

20. The method of claim 17, further comprising:

providing a drive identification responsive to a request.

21. A method for block striping data to or from a plurality of read or write channels, the method comprising:

receiving a logical block address (LBA), an input sector count, and a read or write command;

dividing the received input LBA by the number of channels to compute a quotient result that becomes the new divided result LBA passed to each channel;

determining the modulus of the quotient result from the LBA division operation;

using the division remainder (modulus) to identify the starting channel for a read or write operation;

dividing the received input sector count by the number of channels to compute a quotient result that becomes the new divided sector count for each channel; and

using the sector count division remainder (modulus) to determine the exact sector count for each channel.

22. A method as in claim 21, wherein identifying the selected channel also selects a FIFO buffer for temporarily storing received data before it is sent to the channel.

23. A method as in claim 21, wherein the number of channels is equal to the number of memory modules.

24. A method as in claim 21, wherein the block striping data to or from a plurality of read or write channels is a block striping read operation.

25. A method as in claim 24, further comprising:

communicating the output divided LBA and output divided sector count to the channels;

simultaneously reading from all channels into a FIFO assigned to each channel;

optionally, monitoring status of a FIFO buffer that is interposed between the memory module of the channel and the destination of the read operation and modulating the read operation according to status of the FIFO buffers;

transferring the data from the selected first channel and memory module and associated FIFO buffer to the ATA bus/Host PC; and

repeating the reading, optional monitoring, and transferring from each of the channels until the read operation is complete from all of the channels.

26. A method as in claim 25, wherein the reading from the channels comprises reading from memory modules coupled with the channels.

27. A method as in claim 21, wherein the block striping data to or from a plurality of read or write channels is a block striping write operation.

28. A method as in claim 27, further comprising:

communicating the output divided LBA and output divided sector count to the channels;

writing to a selected first one or the channels until the data reaches a predetermined amount to begin a USB write transaction;

optionally, monitoring status of a FIFO buffer that is interposed between the memory module of the channel and the destination of the read operation and modulating the read operation according to status of the FIFO buffers;

transferring the data from the selected first channel and associated FIFO buffer to the USB Bus and the memory module; and

repeating the reading, optional monitoring, and transferring from each of the channels until the write operation is complete from all of the channels.