SYSTEMS FOR PROGRAMMING NON-VOLATILE MEMORY WITH REDUCED PROGRAM DISTURB BY USING DIFFERENT PRE-CHARGE ENABLE VOLTAGES

• US 20080158991A1
• Filed: 12/29/2006
• Published: 07/03/2008
• Est. Priority Date: 12/29/2006
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Lutze, Jeffrey W., Hemink, Gerrit Jan, Dong, Yingda, Lee, Dana
• Granted Patent: US 7,463,531 B2
• Time in Patent Office: Days
• US Class Current: 365/185.22
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 7/1048 Data bus control circuits, e.g. precharging, presetting, equalising

Abstract

Unselected groups of non-volatile storage elements are boosted during programming to reduce or eliminate program disturb for targeted, but unselected memory cells connected to a selected word line. Prior to applying a program voltage to the selected word line and boosting the unselected groups, the unselected groups are pre-charged to further reduce or eliminate program disturb by providing a larger boosted potential for the unselected groups. During pre-charging, one or more pre-charge enable signals are provided at different voltages for particular non-volatile storage elements.

Claims

1. A non-volatile memory system, comprising:

a group of non-volatile storage elements;

a set of word lines in communication with said group of non-volatile storage elements;

a first subset of word lines on a first side with respect to a particular word line of said set, said first subset has not been subjected to programming when said particular word line is selected for programming;

a second subset of word lines on a second side with respect to said particular word line, said second subset has been subjected to programming when said particular word line is selected for programming; and

managing circuitry in communication with said set of word lines, said managing circuitry pre-charges said group prior to applying a program signal to said particular word line by applying one or more first pre-charge enable signals to said first set and applying one or more second pre-charge enable signals to said second set that are at different voltages than said one or more first pre-charge enable signals, said managing circuitry boosts a channel potential of said group by applying one or more first boosting signals to said first set after applying said one or more first pre-charge enable signals and applying one or more second boosting signals to said second set after applying said one or more second pre-charge enable signals, said one or more first boosting signals are at different voltages than said one or more second boosting signals.

2. The non-volatile memory system of claim 1, wherein said managing circuitry applies a program signal to said particular word line while boosting said group of unselected non-volatile storage elements.

3. The non-volatile memory system of claim 2, wherein:

said program signal is a series of voltage pulses that increase in magnitude.

4. The non-volatile memory system of claim 1, wherein:

a voltage difference between said one or more first boosting signals and said one or more first pre-charge enable signals is substantially equal to a voltage difference between said one or more second boosting signals and said one or more second pre-charge enable signals.

5. The non-volatile memory system of claim 1, wherein:

a voltage difference between said one or more first boosting signals and said one or more first pre-charge enable signals is substantially different than a voltage difference between said one or more second boosting signals and said one or more second pre-charge enable signals.

6. The non-volatile memory system of claim 5, wherein said managing circuitry applies an isolation voltage to a first word line of said set that is adjacent to said particular word line on said second side while applying said first and second boosting signals.

7. The non-volatile memory system of claim 5, wherein said managing circuitry:

applies one or more intermediate voltages to a third subset of one or more word lines that is adjacent to said particular word line on said second side;

applies an isolation voltage to a first word line of said set that is adjacent to said third subset on said second side.

8. The non-volatile memory system of claim 1, wherein said managing circuitry:

applies a third pre-charge enable signal to a first word line of said set that is adjacent to said particular word line on said first side, said first word line has been subjected to partial programming, said third pre-charge enable signal is at a different voltage than said one or more first pre-charge enable signals and said one or more second pre-charge enable signals.

9. The non-volatile memory system of claim 8, wherein said managing circuitry:

applies a fourth pre-charge enable signal to a second word line of said set that is adjacent to said first word line on said first side, said fourth word line has been subjected to partial programming, said fourth pre-charge enable signal is at a same voltage as said third pre-charge enable signal.

10. The non-volatile memory system of claim 1, wherein:

said second subset of one or more word lines includes a first word line that is adjacent to said particular word line and a second word line; and

said managing circuitry applies said one or more second boosting signals by applying a first boosting voltage to said first word line and said second word line.

11. The non-volatile memory system of claim 1, wherein said managing circuitry:

applies a pre-charge voltage to a bit line of said group while applying said first and second pre-charge enable signals and applying said first and second boosting voltages.

12. The non-volatile memory system of claim 1, wherein:

said group of unselected non-volatile storage elements is part of a NAND string having a bit line side and a source line side, said bit line side corresponds to said first side and said source line side corresponds to said second side;

said managing circuitry applies said first and second pre-charge enable signals and said first and second boosting voltages as part of a programming process that applies a program signal in an order that begins with a word line adjacent to a select gate line at said source line side and ends with a word line adjacent to a select gate line at said bit line side.

13. The non-volatile memory system of claim 1, wherein:

said particular word line is connected to an unselected non-volatile storage element of said group that is to be inhibited from programming during application of said program signal;

said selected word line is connected to a selected non-volatile storage element of a different group of non-volatile storage elements that is intended to be programmed.

14. The non-volatile memory system of claim 1, wherein:

said group of unselected non-volatile storage elements is a group of flash memory cells.

15. The non-volatile memory system of claim 14, wherein:

said flash memory cells are multi-state flash memory cells.

16. The non-volatile memory system of claim 1, wherein said managing circuitry includes at least one of row control circuitry, column control circuitry, and a state machine.

17. A non-volatile memory system, comprising:

a group of non-volatile storage elements in communication with a bit line and a source line;

a plurality of word lines in communication with said group including a first set of word lines on said bit line side with respect to a particular non-volatile storage element of said group and a second set of word lines on said source line side with respect to said particular non-volatile storage element;

managing circuitry in communication with said plurality of word lines that applies a first pre-charge enable voltage to each word line of said first set that has been subjected to partial programming, applies a second pre-charge enable voltage to each word line of said first set that has not been subjected to partial programming, and applies a third pre-charge enable voltage to each word line of said second set, said third pre-charge enable voltage is higher than said second pre-charge enable voltage and said second pre-charge enable voltage is lower than said first pre-charge enable voltage.

18. The non-volatile memory system of claim 17, wherein:

said third pre-charge enable voltage is higher than said first pre-charge enable voltage.

19. The non-volatile memory system of claim 17, wherein:

said third pre-charge enable voltage is equal to said first pre-charge enable voltage.

20. The non-volatile memory system of claim 17, wherein said managing circuitry:

applies a first boosting voltage to each word line of said first set that has been subjected to partial programming after applying said first pre-charge enable voltage;

applies a second boosting voltage to each word line of said first set that has not been subjected to programming after applying said second pre-charge enable voltage; and

applies a third boosting voltage to each word line of said second set after applying said third pre-charge enable voltage.

21. The non-volatile memory system of claim 20, wherein:

a difference between said first boosting voltage and said first pre-charge enable voltage is substantially equal to a difference between said second boosting voltage and said second pre-charge enable voltage; and

a difference between said third boosting voltage and said third pre-charge enable voltage is substantially equal to said difference between said first boosting voltage and said first pre-charge enable voltage.

22. A non-volatile memory system, comprising:

a group of non-volatile storage elements in communication with a bit line and a source line;

a plurality of word lines in communication with said group, said plurality of word lines includes a particular word line, a first set of one or more word lines on said bit line side of said group with respect to said particular word line and a second set of two or more word lines on said source line side of said group with respect to said particular word line, said first set has not been subjected to programming and said second set has been subjected to programming when said particular word line is selected for programming;

managing circuitry in communication with said plurality of word lines that pre-charges said group when said storage elements are to be inhibited from programming during application of a program signal to said particular word line, said managing circuitry pre-charges said group by applying a pre-charge voltage to said bit line, applying a first voltage to said first set of one or more word lines while applying said pre-charge voltage, and applying a second voltage to said second set of two or more word lines while applying said pre-charge voltage, said second voltage is lower than said first voltage, said managing circuitry applies a program voltage to said selected word line after applying said first voltage and said second voltage and applies one or more boosting voltages to said first set of word lines and said second set of word lines while applying said program voltage.

23. The non-volatile memory system of claim 22, wherein said managing circuitry applies a third voltage to a third set of word lines on said bit line side of said group while applying said pre-charge voltage, said third set has been subjected to partial programming.

24. The non-volatile memory system of claim 22, wherein said third voltage is lower than said second voltage.

25. The non-volatile memory system of claim 22, wherein:

said group of unselected non-volatile storage elements is a group of flash memory cells.