METHOD, APPARATUS, AND SYSTEM FOR IMPROVED ERASE OPERATION IN FLASH MEMORY

• US 20080159009A1
• Filed: 12/28/2006
• Published: 07/03/2008
• Est. Priority Date: 12/28/2006
• Status: Active Grant

• Current Assignee: Intel NDTM US LLC (Intel Corporation)
• Original Assignee: Intel Corporation
• Inventors: Aritome, Seiichi
• Granted Patent: US 7,539,066 B2
• Time in Patent Office: Days
• US Class Current: 365/185.29
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/344 Arrangements for verifying correct erasure or for detecting overerased cells

Abstract

Various embodiments include erasing at least one memory cell of a string of memory cells of a memory device while a control gate of at least one of a first memory cell and a second memory cell of the string of memory cells has a first voltage and while a control gate of each memory cell of a plurality of intermediate memory cells between the first memory cell and the second memory cell has a second voltage. Some embodiments include erase verifying only the first memory cell and second memory cell in a first erase verify operation, and erase verifying the plurality of intermediate memory cells in a second erase verify operation. Other embodiments including additional apparatus, systems, and methods are disclosed.

Claims

1. A method comprising:

erasing at least one memory cell of a string of memory cells of a memory device while a control gate of at least one of a first memory cell and a second memory cell of the string of memory cells has a first voltage and while a control gate of each memory cell of a plurality of intermediate memory cells of the string of memory cells has a second voltage, the plurality of intermediate memory cells being located between the first memory cell and the second memory cell.

2. The method of claim 1, wherein erasing includes erasing only the plurality of intermediate memory cells when the second voltage is lower than the first voltage.

3. The method of claim 2, wherein erasing includes erasing only the first memory cell and the second memory cell when the second voltage is greater than the first voltage.

4. The method of claim 3, wherein the second voltage is ground when only the plurality of intermediate memory cells is erased, and wherein the first voltage is ground when only the first memory cell and the second memory cell are erased.

5. The method of claim 4, wherein the first voltage is about one volt to about five volts when only the plurality of intermediate memory cells is erased, and wherein the second voltage is about one volt to about five volts when only the first memory cell and the second memory cell are erased.

6. The method of claim 3, wherein the plurality of intermediate memory cells is erased before the first memory cell and the second memory cell are erased.

7. The method of claim 3, wherein the plurality of intermediate memory cells is erased after the first memory cell and the second memory cell are erased.

8. The method of claim 1 further comprising:

applying an erase voltage to a well of the memory device, wherein at least a portion of the string of memory cells is formed on the well; and

floating a gate of a select transistor coupled between the string of memory cells and one of a bit line and a source line of the memory device, the string of memory cells being coupled between the bit line and the source line.

9. The method of claim 1 further comprising:

applying an erase voltage to a well of the memory device, wherein at least a portion of the string of memory cells is formed on the well; and

floating a gate of at least one select transistor coupled between a bit line and a source line of the memory device, wherein the string of memory cells is coupled between bit line and the source line.

10. The method of claim 1 further comprising:

erase verifying only the first memory cell and second memory cell in a first erase verify operation; and

erase verifying the plurality of intermediate memory cells in a second erase verify operation.

11. The method of claim 10, wherein erasing the at least one memory cell includes erasing the first memory cell and the second memory cell before erasing the plurality of intermediate memory cells, wherein the first erase verify operation is performed before the second erase verify operation, and wherein the second erase verify operation is performed only when the first erase verify operation indicates a successful result.

12. The method of claim 10, wherein erasing the at least one memory cell includes erasing the first memory cell and the second memory cell after erasing the plurality of intermediate memory cells, wherein the first erase verify operation is performed after the second erase verify operation, and wherein the first erase verify operation is performed only when the second erase verify operation indicates a successful result.

13. The method of claim 10 further comprising:

repeating the erasing of the at least one memory cell of the string of memory cells of the memory device while the control gate of at least one of the first memory cell and the second memory cell of the string of memory cells has the first voltage and while the control gate of each memory cell of the plurality of intermediate memory cells has the second voltage, wherein repeating is performed when one of the first and second erase verify operations indicates an unsuccessful result.

14. The method of claim 13, wherein the second voltage is greater than the first voltage, and wherein repeating the erasing includes erasing only at least one of the first memory cell and the second memory cell.

15. An apparatus comprising:

a string of memory cells including a first memory cell, a second memory cell, and a plurality of intermediate memory cells coupled between the first memory cell and the second memory cell; and

a circuit to erase at least one memory cell of the string of memory cells while a first control gate of at least one of the first and second memory cells has a first voltage and while a second control gate of each memory cell of the plurality of intermediate memory cells has a second voltage.

16. The apparatus of claim 15 further comprising a well, a bit line, and a select transistor coupled between the first memory cell and the bit line, wherein at least a portion of at least one memory cell of the string of memory cells is formed on the well.

17. The apparatus of claim 16 further comprising a source line, and a second select transistor coupled between the second memory cell and the source line.

18. The apparatus of claim 15, wherein the circuit is to erase only the plurality of intermediate memory cells when the second voltage is lower than the first voltage, and to erase only the first memory cell and the second memory cell when the second voltage is greater than the first voltage.

19. The apparatus of claim 18, wherein the circuit is to hold the second voltage at ground when only the plurality of intermediate memory cells is erased, and to hold the first voltage at ground when only the first memory cell and the second memory cell are erased.

20. The apparatus of claim 15 further comprising a well, a bit line, a source line, a first select transistor coupled between the bit line and the string of memory cells, a second select transistor coupled between the source line and the string of memory cells, wherein at least a portion of at least one memory cell of the string of memory cells is formed on the well, wherein the circuit is to apply an erase voltage to the well, and wherein the circuit is to float a gate of at least one of the first and second select transistors when at least one memory cell of the string of memory cells is erased.

21. The apparatus of claim 15, wherein the circuit is to erase verify only the first memory cell and the second memory cell in a first erase verify operation, and to erase verify the plurality of intermediate memory cells in a second erase verify operation.

22. The apparatus of claim 21, wherein the circuit is to cause the second erase verify operation to be performed only when the first erase verify operation indicates a successful result.

23. The apparatus of claim 21, wherein the circuit is to cause the first erase verify operation to be performed only when the second erase verify operation indicates a successful result.

24. The apparatus of claim 21, wherein the circuit is to repeat the erasing at least one memory cell of the string of memory cells of the memory device while the first control gate of at least one of the first memory cell and the second memory cell of the string of memory cells has the first voltage and while the second control gate of each memory cell of the plurality of intermediate memory cells has the second voltage, wherein the circuit is to repeat erasing when one of the first and second erase verify operations indicates an unsuccessful result.

25. A system comprising:

a flash memory device including a string of memory cells with a first memory cell, a second memory cell, and plurality of intermediate memory cells coupled between the first memory cell and the second memory cell, and a circuit to erase at least one memory cell of the string of memory cells of a memory device while a first control gate of at least one of the first and second memory cells has a first voltage and while a second control gate of each memory cell of the plurality of intermediate memory cells has a second voltage; and

a circuit board coupled to the flash memory device, the circuit board including a terminal to couple to a battery to provide a voltage to the flash memory device.

26. The system of claim 25 further comprising a well, a bit line, a source line, a first select transistor coupled between the bit line and the string of memory cells, a second select transistor coupled between the source line and the string of memory cells, wherein at least a portion of at least one memory cell of the string of memory cells is formed on the well, wherein the circuit is to apply an erase voltage to the well, and wherein the circuit is to float a gate of at least one of the first and second select transistors when at least one memory cell of the string of memory cells is erased.

27. The system of claim 26, wherein the circuit is to is to erase verify only the first memory cell and second memory cell in a first erase verify operation, and to erase verify the plurality of intermediate memory cells in a second erase verify operation.