Memory access without internal microprocessor intervention

• US 20080162835A1
• Filed: 01/03/2007
• Published: 07/03/2008
• Est. Priority Date: 01/03/2007
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Wilson, Thomas James, Hori, Yutaka
• Granted Patent: US 8,510,481 B2
• Time in Patent Office: Days
• US Class Current: 711/155
• CPC Class Codes: G06F 3/04164 Connections between sensors and controllers, e.g. routing lines between electrodes and connection pads
• CPC Class Codes: G06F 3/04166 Details of scanning methods, e.g. sampling time, grouping of sub areas or time sharing with display driving Synchronisation with the driving of the display or the backlighting unit to avoid interferences generated internally G06F3/04184

Abstract

A method and system for accessing a computer system memory without processor intervention is disclosed. In one embodiment, the method includes initiating a predetermined communication protocol between a first device and a second device, the first device including a first processor, a first memory and a first communication interface, the second device including a second processor, a second memory and a second communication interface. The predetermined communication protocol enables an access operation to be performed on the first or second memory without intervention by the first or second processor. In one embodiment, the predetermined communication protocol utilizes a plurality of predefined packet types which are identified by a packet header decoder.

Claims

1. A computer system, comprising:

a sensor panel;

a first device configured to receive and process sense signals from the sensor panel, the first device including a first processor, a first memory and a first communication interface; and

a second device, external to the first device, including a second processor, a second memory and a second communication interface, wherein the first and second devices communicate via the first and second communication interfaces implementing a predetermined communication protocol that enables an access operation to be performed on the first or second memory without intervention by the first processor.

2. The computer system of claim 1, wherein the predetermined communication protocol comprises a packet-based communication protocol that includes a plurality of packet types each having a predefined header format.

3. The computer system of claim 2 wherein the first communication interface comprises:

a packet header decoder for identifying a packet type corresponding to a packet transmitted between the first and second communication interfaces; and

a logic device for executing instructions corresponding to the packet type without intervention by the first processor.

4. The computer system of claim 1 wherein the first communication interface comprises a first serial peripheral interface and the second communication interface comprises a second serial peripheral interface.

5. The computer system of claim 1 wherein the access operation comprises storing a boot program from the second memory to the first memory.

6. The computer system of claim 1 wherein the access operation comprises the second device reading data stored in the first memory.

7. The computer system of claim 1 wherein the access operation comprises the second device writing data to the first memory.

8. The computer system of claim 1 wherein the access operation comprises a read-modify-write operation.

9. The computer system of claim 1 wherein the access operation comprises storing processed sense signals into the second memory.

10. The computer system of claim 9 wherein the second device comprises a host device, the second processor comprises a host processor and the second memory comprises a host memory of the system, wherein the host processor receives and further processes the processed sense signals from the first device and executes system functions based on the processed sense signals.

11. The computer system of claim 1 wherein the system is embodied in a mobile telephone.

12. The computer system of claim 1 wherein the system is embodied in a digital audio player.

13. A computer system, comprising:

a first device including a first processor, a first memory and a first communication interface;

a second device, external to the first device, including a second processor, a second memory and a second communication interface, wherein the first and second devices communicate via the first and second communication interfaces implementing a predetermined packet-based communication protocol that utilizes a plurality of packet types each having a predefined header format;

a packet header decoder for identifying a packet type corresponding to a packet transmitted between the first and second communication interfaces; and

a logic device contained within the first communication interface configured to be responsive to the packet type and execute an access operation to be performed on the first or second memory without intervention by the first processor.

14. The computer system of claim 13 wherein the first communication interface comprises a first serial peripheral interface and the second communication interface comprises a second serial peripheral interface.

15. The computer system of claim 13 wherein the access operation comprises storing a boot program from the second memory to the first memory.

16. The computer system of claim 13 wherein the access operation comprises the second device reading data stored in the first memory.

17. The computer system of claim 13 wherein the access operation comprises the second device writing data to the first memory.

18. The computer system of claim 13 wherein the access operation comprises a read-modify-write operation performed on data stored in the first memory.

19. The computer system of claim 13 wherein the logic device comprises a micro-sequencer configured to execute micro-instructions based on the packet type.

20. The computer system of claim 13 wherein the system is embodied in a mobile telephone.

21. The computer system of claim 13 wherein the system is embodied in a digital audio player.

22. A method of accessing a computer system memory, comprising:

initiating a predetermined communication protocol between a first device and a second device, the first device including a first processor, a first memory and a first communication interface, the second device including a second processor, a second memory and a second communication interface, and

wherein the predetermined communication protocol enables an access operation to be performed on the first or second memory without intervention by the first or second processor.

23. The method of claim 22 wherein the predetermined communication protocol comprises a packet-based communication protocol that includes a plurality of packet types each having a predefined header format.

24. The method of claim 23 further comprising:

identifying a packet type corresponding to a packet transmitted between the first and second communication interfaces; and

executing instructions corresponding to the packet type without intervention by the first or second processor.

25. The method of claim 22 wherein the access operation comprises storing a boot program from the second memory to the first memory.

26. The method of claim 22 wherein the access operation comprises the second device reading data stored in the first memory.

27. The method of claim 22 wherein the access operation comprises the second device writing data to the first memory.

28. The method of claim 22 wherein the access operation comprises a read-modify-write operation.

29. The method of claim 22 wherein the access operation comprises storing processed sense signals received by the first device from a touch surface device into the second memory.

30. A computer system, comprising:

means for initiating a predetermined communication protocol between a first device and a second device, the first device including a first processor, a first memory and a first communication interface, the second device including a second processor, a second memory and a second communication interface, and

wherein the predetermined communication protocol utilizes a plurality of packet types each having a predefined header format and enables an access operation to be performed on the first or second memory without intervention by the first or second processor.

31. The system of claim 30 further comprising:

means for identifying a packet type corresponding to a packet transmitted between the first and second communication interfaces; and

means for executing instructions corresponding to the packet type without intervention by the first or second processor.

32. The system of claim 30 wherein the access operation comprises storing a boot program from the second memory to the first memory.

33. The system of claim 30 wherein the access operation comprises the second device reading data stored in the first memory.

34. The system of claim 30 wherein the access operation comprises the second device writing data to the first memory.

35. The system of claim 30 wherein the access operation comprises a read-modify-write operation.

36. The system of claim 30 wherein the access operation comprises storing processed sense signals received by the first device from a touch surface device into the second memory.

37. A mobile telephone, comprising:

a sensor panel;

a first device configured to receive and process sense signals from the sensor panel, the first device including a first processor, a first memory and a first communication interface; and

a second device, external to the first device, including a second processor, a second memory and a second communication interface, wherein the first and second devices communicate via the first and second communication interfaces implementing a predetermined communication protocol that enables an access operation to be performed on the first or second memory without intervention by the first processor.

38. A digital audio player, comprising:

a sensor panel;

a first device configured to receive and process sense signals from the sensor panel, the first device including a first processor, a first memory and a first communication interface; and

a second device, external to the first device, including a second processor, a second memory and a second communication interface, wherein the first and second devices communicate via the first and second communication interfaces implementing a predetermined communication protocol that enables an access operation to be performed on the first or second memory without intervention by the first processor.