Methods and Systems for Time Keeping in a Data Processing System

• US 20080168201A1
• Filed: 01/07/2007
• Published: 07/10/2008
• Est. Priority Date: 01/07/2007
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Smith, Michael, de Cesare, Joshua, Semeria, Bernard
• Granted Patent: US 8,667,198 B2
• Time in Patent Office: Days
• US Class Current: 710/260
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 13/24 using interrupt G06F13/32 takes precedence
• CPC Class Codes: G06F 13/36 for access to common bus or bus system
• CPC Class Codes: G06F 9/4825 Interrupt from clock, e.g. time of day
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Data processing systems with interrupts and methods for operating such data processing systems and machine readable media for causing such methods and containing executable program instructions. In one embodiment, an exemplary data processing system includes a processing system, an interrupt controller coupled to the processing system and a timer circuit which is coupled to the interrupt controller. The interrupt controller is configured to provide a first interrupt signal and a second interrupt signal to the processing system. The processing system is configured to maintain a data structure (such as, e.g., a list) of time-related events for a plurality of processes, and the processing system is configured to cause the entry of a value, representing a period of time, into the timer circuit. The timer circuit is configured to cause an assertion of the first interrupt signal in response to an expiration of the time period.

Claims

1. A data processing system comprising:

a processing system;

an interrupt controller coupled to the processing system to provide a first interrupt signal and a second interrupt signal to the processing system;

a timer circuit coupled to the interrupt controller, the processing system configured to maintain a data structure of time-related events for a plurality of processes and the processing system configured to cause the entry of a value, representing a period of time, into the timer circuit, and the timer circuit configured to cause an assertion of the first interrupt signal in response to an expiration of the period of time, and the processing system configured to cause the entry in response to selecting a time-related event from the data structure.

2. The data processing system as in claim 1 wherein the first interrupt signal is a fast interrupt signal and the second interrupt signal is a normal interrupt signal.

3. The data processing system as in claim 1 wherein the plurality of processes comprise software processes for a corresponding plurality of hardware subsystems.

4. The data processing system as in claim 3 wherein the corresponding plurality of hardware subsystems comprise at least two of (a) a data codec;

(b) a digital signal processor;

(c) the processing system;

(d) a graphics processing unit;

(e) a display controller;

(f) a wireless interface controller;

(g) a camera interface controller; and

(h) a serial bus interface controller.

5. The data processing system of claim 1 wherein the processing system, the interrupt controller and the timer circuit are disposed on a monolithic semiconductor substrate which is a system on a chip (SOC), and wherein the graphics processing unit, at least one peripheral interface controller, at least one memory controller, and at least one codec are also disposed on the monolithic semiconductor substrate, and wherein the processing system is a microprocessor.

6. The data processing system of claim 4 wherein at least one of the hardware subsystems are powered up from a reduced power state in response to the assertion of the first interrupt signal.

7. The data processing system of claim 1 wherein the time-related event is an event which represents an action to be performed at or after a time or period of time.

8. The data processing system of claim 1 wherein the processing system causes the entry of the value in response to determining that the processing system will enter a reduced power state and wherein the entry occurs before the processing system enters the reduced power state.

9. The data processing system of claim 1 wherein if interrupts are disabled when the first interrupt signal is asserted then the first interrupt signal is converted to the second interrupt signal.

10. The data processing system of claim 1 wherein after the value is entered into the timer circuit, the timer circuit causes assertion of the first interrupt signal without executing operating system software which is controlling the processing system.

11. A data processing system comprising:

a processing system;

an interrupt controller coupled to the processing system to provide a first interrupt signal to the processing system and to provide a second interrupt signal to the processing system, wherein the first interrupt signal receives a higher priority service from the processing system than the second interrupt signal;

a timing circuit coupled to the interrupt controller, the processing system con figured to maintain a data structure of time-related events for a plurality of processes of different subsystems of the data processing system, wherein the processing system is configured to cause the timing circuit to specify a time, and wherein the timing circuit is configured to cause an assertion of the first interrupt signal in response to the time, and wherein the processing system is configured to cause the timing circuit to specify the time in response to selecting a time-related event from the data structure.

12. The data processing system of claim 11 wherein the plurality of processes comprise software processes for a corresponding plurality of hardware subsystems which comprise at least two of (a) a data codec;

(b) a digital signal processor;

(c) the processing system;

(d) a graphics processing unit;

(e) a display controller;

(f) a wireless interface controller;

(g) a camera interface controller; and

(h) a serial bus interface controller.

13. The data processing system of claim 12 wherein at least one of the hardware subsystems are powered up from a reduced power state in response to the assertion of the first interrupt signal.

14. The data processing system of claim 11 wherein after the timing circuit has been configured to specify a time, the timing circuit causes assertion of the first interrupt signal without executing operating system software which is controlling the processing system, and wherein the timing circuit specifies the time in the form of a time period represented by a counter value or a real time in the future.

15. A machine implemented method comprising:

selecting a time-related event from a data structure of time-related events for a plurality of processes of different subsystems;

setting a timing circuit to specify a time in response to the selecting;

asserting a first interrupt signal in response to the time occurring, wherein the timing circuit causes the assertion of a first interrupt signal by an interrupt controller.

16. The method of claim 15 wherein the time is represented by one of a period of time or a real time in the future.

17. The method of claim 16 wherein the interrupt controller also provides a second interrupt signal which receives a lower priority service from a processing system which receives both the first interrupt signal and the second interrupt signal.

18. The method of claim 16 wherein the plurality of processes comprise software processes for a corresponding plurality of hardware subsystems which comprise at least two of (a) a data codec;

(b) a digital signal processor;

(c) a processing system;

(d) a graphics processing unit;

(e) a display controller;

(f) a wireless interface controller;

(g) a camera interface controller; and

(h) a serial bus interface controller.

19. The method of claim 18 wherein at least one of the hardware subsystems are powered up from a reduced power state in response to the assertion of the first interrupt signal.

20. A machine readable medium containing executable program instructions which cause a data processing system to perform a method comprising:

selecting a time-related event from a data structure of time-related events for a plurality of processes of different subsystems;

setting a timing circuit to specify a time in response to the selecting;

asserting a first interrupt signal in response to the time occurring, wherein the timing circuit causes the assertion of a first interrupt signal by an interrupt controller.

21. The medium of claim 20 wherein the time is represented by one of a period of time or a real time in the future.

22. The medium of claim 21 wherein the interrupt controller also provides a second interrupt signal which receives a lower priority service from a processing system which receives both the first interrupt signal and the second interrupt signal.

23. The medium of claim 21 wherein the plurality of processes comprise software processes for a corresponding plurality of hardware subsystems which comprise at least two of (a) a data codec;

(b) a digital signal processor;

(c) a processing system;

(d) a graphics processing unit;

(e) a display controller;

(f) a wireless interface controller;

(g) a camera interface controller; and

(h) a serial bus interface controller.

24. The medium of claim 23 wherein at least one of the hardware subsystems are powered up from a reduced power state in response to the assertion of the first interrupt signal.

25. A data processing system comprising:

means for selecting a time-related event from a data structure of time-related events for a plurality of processes of different subsystems;

means for setting a timing circuit to specify a time in response to the selecting;

means for asserting a first interrupt signal in response to the time occurring, wherein the timing circuit causes the assertion of a first interrupt signal by an interrupt controller.