METHOD AND STRUCTURE FOR FABRICATING SOLAR CELLS USING A THICK LAYER TRANSFER PROCESS

• US 20080179547A1
• Filed: 09/07/2007
• Published: 07/31/2008
• Est. Priority Date: 09/08/2006
• Status: Active Grant

• Current Assignee: Silicon Genesis
• Original Assignee: Silicon Genesis
• Inventors: Henley, Francois J.
• Granted Patent: US 7,811,900 B2
• Time in Patent Office: Days
• US Class Current: 250/492.21
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• CPC Class Codes: H01L 31/03921 including only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 31/068 the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
• CPC Class Codes: H01L 31/0687 Multiple junction or tandem solar cells
• CPC Class Codes: H01L 31/1804 comprising only elements of Group IV of the Periodic Table
• CPC Class Codes: Y02E 10/544 Solar cells from Group III-V materials
• CPC Class Codes: Y02E 10/547 Monocrystalline silicon PV cells
• CPC Class Codes: Y02P 70/50 Manufacturing or production processes characterised by the final manufactured product

Abstract

A photovoltaic cell device, e.g., solar cell, solar panel, and method of manufacture. The device has an optically transparent substrate comprises a first surface and a second surface. A first thickness of material (e.g., semiconductor material, single crystal material) having a first surface region and a second surface region is included. In a preferred embodiment, the surface region is overlying the first surface of the optically transparent substrate. The device has an optical coupling material provided between the first surface region of the thickness of material and the first surface of the optically transparent material.

Claims

1. A method for fabricating a photovoltaic cell using a large scale implant process, the method comprising:

providing a tile shaped semiconductor substrate, the tile shaped semiconductor substrate having a surface region, a cleave region and a first thickness of material to be removed between the surface region and the cleave region;

introducing through the surface region a plurality of hydrogen particles operable in substantially a protonic mode within a vicinity of the cleave region using a high energy implantation process;

coupling the surface region of the tile shaped semiconductor substrate to a first surface region of a substrate, the substrate comprising the first surface region and a second surface region;

cleaving the semiconductor substrate to remove the first thickness of material from the tile shaped semiconductor substrate; and

forming a solar cell from at least first thickness of material characterized by the tile shape overlying the substrate.

2. The method of claim 1 further comprising plasma activating the surface region and the first surface region before coupling the surface region to the first surface region.

3. The method of claim 1 wherein the coupling comprises an optical coupling material between the surface region and the first surface region.

4. The method of claim 1 wherein the optical coupling material comprises silicon nitride, silicon carbide, tin oxide, indium tin oxide, or titanium dioxide.

5. The method of claim 1 wherein the optical coupling material comprises a dielectric stack.

6. The method of claim 1 further comprising forming a second thickness of semiconductor material comprises a solid phase epitaxy process overlying the first thickness of material.

7. The method of claim 1 further comprising forming of a second thickness of semiconductor material comprises forming an amorphous silicon layer overlying the first thickness of material.

8. The method of claim 7 further comprises crystallizing the amorphous silicon layer.

9. The method of claim 1 further comprising forming a second thickness of semiconductor material comprises an epitaxial growth process overlying the first thickness of material.

10. The method of claim 9 where the epitaxial growth process is selected from hot-wire CVD, plasma-enhanced CVD, ion-bean assisted deposition, and thermal CVD epitaxial growth.

11. The method of claim 1 wherein the first thickness of semiconductor material comprises a single crystal silicon material.

12. The method of claim 1 wherein the first thickness of semiconductor material comprises polycrystalline silicon material.

13. The method of claim 1 wherein the substrate comprises a glass substrate or a quartz substrate.

14. The method of claim 1 wherein the substrate comprises a conductive material including tin oxide and indium tin oxide.

15. The method of claim 1 wherein the first thickness of material comprises one or more photovoltaic regions, the one or more photovoltaic regions comprising a first electrode and a second electrode.

16. The method of claim 1 wherein the cleaving comprises a controlled cleaving process.

17. The method of claim 1 wherein the cleaving comprises a thermal cleaving process.

18. The method of claim 1 wherein hydrogen particle introduction occurs while the tile shaped semiconductor substrate is at a temperature range between about 200 to 850 centigrade or 300 to 600 centigrade.

19. The method of claim 1 wherein the cleaving comprises an initiation process and a propagation process to free the first thickness of material from a remaining portion of the tile shaped semiconductor substrate.

20. The method of claim 1 wherein the surface region is substantially a face of the tile shaped semiconductor substrate.

21. The method of claim 1 wherein the surface region is characterized by an overlying masking layer.

22. The method of claim 21 wherein the masking layer is around a periphery of the surface region.

23. The method of claim 1 wherein the hydrogen particles are provided in H⁺ mode.

24. The method of claim 1 wherein the hydrogen particles are provided in H²⁺ mode and/or H³⁺ mode.

25. The method of claim 1 wherein the high energy implantation process uses substantially non-mass selected H⁺ at an energy ranging from about 300 keV to 2.1 MeV.

26. The method of claim 25 wherein the high energy substantially non-mass selected implantation process provides the first thickness of silicon material suitable for ranging from about 3 um to about 50 um

27. The method of claim 1 wherein the high energy implantation process uses H⁺ at an energy ranging from about 2.1 MeV to 5 MeV.

28. The method of claim 27 wherein the high energy implantation process provides the first thickness of silicon material ranging from about 50 um to about 220 um.

29. The method of claim 27 wherein the first thickness of semiconductor material is provided free of a handler substrate.

30. The method of claim 1 wherein the tile shaped semiconductor substrate comprises an overlying dielectric layer to prevent co-implant of contaminants, the overlying dielectric layer acting as a screen layer.

31. The method of claim 30 wherein the overlying dielectric layer is silicon dioxide.

32. The method of claim 30 wherein the overlying dielectric layer is removed after the implantation process.

33. The method of claim 30 wherein the overlying dielectric layer is not removed after the implantation process.

34. The method of claim 1 wherein the surface region of the first thickness of material is attached to a backing substrate, exposing a backside surface region of the first thickness of material.

35. The method of claim 34 wherein the backing substrate is temporarily attached to the first thickness of material.

36. The method of claim 35 wherein the backing substrate is temporarily attached to the first thickness of material using a vacuum or electrostatic means.

37. The method of claim 35 wherein the backing substrate is temporarily attached to the first thickness of material using a releasable adhesive.

38. The method of claim 34 wherein the backing substrate is permanently attached to the first thickness of material.

39. A method of fabricating a solar cell, the method comprising:

providing a semiconductor substrate having a lattice orientation normal to a major surface and a plurality of gettering sites or defect regions formed in a subsurface cleave plane by implantation of hydrogen; and

applying energy from a beam to impart fracture stress at the cleave plane and perform a controlled cleaving process to release a free standing film.

40. The method of claim 39 wherein a direction of the lattice normal to the semiconductor substrate surface being implanted is <

100>

.

41. The method of claim 40 wherein the controlled cleaving process occurs with a reduced possibility of cleave failure if the direction of the lattice normal to the semiconductor substrate surface being implanted is <

110>

.

42. The method of claim 39 wherein the direction of the lattice normal to the semiconductor substrate surface being implanted is <

110>

.

43. The method of claim 42 wherein a lower implant dose of implanted hydrogen to create the plurality of gettering sites of defect regions is required than if the direction of the lattice normal to the semiconductor substrate surface being implanted is <

100>

.

44. The method of claim 39 wherein heating from an ion beam applied the semiconductor substrate imparts the fracture stress.

45. The method of claim 44 wherein the ion beam comprises the hydrogen whose implantation creates the gettering sites or defect regions.

46. The method of claim 39 wherein a beam of thermal energy is applied to impart the fracture stress to the semiconductor substrate.

47. The method of claim 46 wherein the beam of thermal energy comprises a laser beam.

48. The method of claim 46 wherein heating from the beam of thermal energy creates a thermal gradient in a direction of the cleave plane that imparts the fracture stress.

49. The method of claim 48 wherein the thermal beam is scanned in a direction along the cleave plane.

50. The method of claim 48 further comprising applying a cold plate to minimize asymmetry in a thermal gradient in a direction perpendicular to the cleave plane.

51. The method of claim 46 wherein heating from the bream of thermal energy creates a thermal gradient and a corresponding shear force in a direction perpendicular to the cleave plane, the shear force imparting the fracture stress.

52. The method of claim 46 wherein the thermal beam is applied to a surface of the semiconductor substrate bearing a liquid layer, such that a shock wave resulting from generation of a plasma by impact of the thermal beam, is confined by the water and directed to the cleave plane to impart the tensile strain.

53. The method of claim 52 wherein the liquid layer comprises water.

54. The method of claim 52 wherein the surface comprises a surface of the second substrate.

55. A method of fabricating a solar cell, the method comprising:

providing a semiconductor substrate having a plurality of gettering sites or defect regions formed in a subsurface cleave plane; and

applying energy to the semiconductor substrate from a thermal beam to impart fracture stress in a direction along the cleave plane and perform a controlled cleaving process to release a free standing film.

56. The method of claim 55 further comprising scanning the thermal beam in a direction to extend a cleave front along the cleave plane.

57. A method of fabricating a solar cell, the method comprising:

providing a semiconductor substrate having a plurality of gettering sites or defect regions formed in a subsurface cleave plane; and

applying energy to the semiconductor substrate from a thermal beam to impart a thermal gradient and a shear force in a direction perpendicular to the cleave plane and perform a controlled cleaving process to release a free standing film.

58. A method of fabricating a solar cell, the method comprising:

applying an ion beam to a semiconductor substrate to form a subsurface cleave plane having a plurality of gettering sites or defect regions, wherein thermal energy from the ions creates a thermal gradient and a fracture stress, such that a controlled cleaving process is performed to release a free standing film.

59. A method of fabricating a solar cell, the method comprising:

providing a semiconductor substrate having a surface layer of water and a plurality of gettering sites or defect regions formed in a subsurface cleave plane; and

applying laser energy to the semiconductor substrate to create a plasma confined by the water layer, such that a shock wave from the plasma imparts a fracture stress at the cleave plane to perform a controlled cleaving process to release a free standing film.

60. An assembly comprising:

a reusable donor substrate in the form of a bulk ingot or boule of semiconductor material, the reusable donor substrate having a surface and a plurality of subsurface gettering sites or defect regions, the surface of the reusable donor substrate bonded to a final substrate.

61. The assembly of claim 60 further comprising a plurality of reusable donor substrates bonded to a common final substrate.

62. The assembly of claim 60 wherein the final substrate is transparent to incident light.

63. The assembly of claim 60 wherein the final substrate is transparent to incident light.

64. The assembly of claim 60 wherein a direction of a lattice of the semiconductor material normal to the surface is <

100>

.

65. The assembly of claim 60 wherein a direction of a lattice of the semiconductor material normal to the surface is <

110>

.

66. A system comprising:

an ion source in vacuum communication with a surface of a reusable donor substrate in the form of a bulk ingot or boule of a semiconductor material, the ion source configured to implant hydrogen ions into the surface to create a plurality of subsurface gettering sites or defect regions.

67. The system of claim 66 wherein a direction of a lattice of the bulk semiconductor material normal to the surface is <

100>

.

68. The system of claim 66 wherein a direction of a lattice of the bulk semiconductor material normal to the surface is <

110>

.

69. The system of claim 66 further comprising a screening layer overlying the surface and configured to block any contamination from the ion source.

70. The system of claim 66 further comprising a rigid plate in contact with the surface and configured to confine a free standing layer released from the bulk semiconductor material by the implantation.