Method of manufacturing an imprinting template using a semiconductor manufacturing process and the imprinting template obtained

• US 20080182070A1
• Filed: 01/31/2007
• Published: 07/31/2008
• Est. Priority Date: 01/31/2007
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Liao, Jiunn-Hsiung, Chou, Pei-Yu
• Granted Patent: US 7,846,345 B2
• Time in Patent Office: Days
• US Class Current: 428/138
• CPC Class Codes: B81C 99/009 Manufacturing the stamps or the moulds
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: B82Y 40/00 Manufacture or treatment of nanostructures
• CPC Class Codes: G03F 7/0002 Lithographic processes using patterning methods other than those involving the exposure to radiation, e.g. by stamping
• CPC Class Codes: H01L 2933/0083 Periodic patterns for optical field-shaping in or on the semiconductor body or semiconductor body package, e.g. photonic bandgap structures
• CPC Class Codes: H01L 33/44 characterised by the coatings, e.g. passivation layer or anti-reflective coating
• CPC Class Codes: Y10T 428/24331 including nonapertured component

Abstract

The method of manufacturing an imprinting template according to the present invention utilizes a semiconductor manufacturing process and comprises a step of etching an oxide layer having a thickness of from 1000 to 8000 angstroms on a substrate by a microlithography and etching process, to form a pattern having a plurality of pillar-shaped holes, thereby forming an imprinting plate having a plurality of pillar-shaped holes. A material layer may be filled into the holes and a part of the oxide layer is removed to form an imprinting template having a plurality of pillar-shaped protrusions. Alternatively, a silicon substrate may be used instead of the substrate and the oxide layer. The imprinting template according to the present invention has advantages of mass production, fast production, and low cost, and is suitable to serve as the imprinting plate for making photonic crystals.

Claims

1. A method of manufacturing an imprinting template using a semiconductor manufacturing process, comprising:

providing a substrate;

forming an oxide layer having a thickness in a range of 1000 angstroms to 8000 angstroms on the substrate;

forming a photoresist layer on the oxide layer;

performing a microlithography and etch process on the photoresist layer to form a pattern having a plurality of contact hole-like openings;

etching the oxide layer through the openings to form a plurality of pillar-shaped holes; and

removing the photoresist layer, thereby forming an imprinting template having a plurality of pillar-shaped holes.

2. The method of claim 1, wherein the pillar-shaped holes are regularly and periodically arranged in a pitch of micro dimension, sub-micro dimension, or nano dimension.

3. The method of claim 1, wherein the substrate comprises silicon.

4. The method of claim 1, wherein the oxide layer comprises silicon dioxide.

5. The method of claim 1, wherein the oxide layer is formed by a thermal oxidation process or a chemical vapor deposition process.

6. The method of claim 1, further comprising forming a cap layer over the oxide layer.

7. The method of claim 1, wherein etching the oxide layer is stopped on the surface of the substrate or further etching the substrate.

8. The method of claim 1, wherein the step of forming the oxide layer is paused, an intermediate layer is further formed on the paused oxide layer, and the step of forming the oxide layer is continued on the intermediate layer.

9. The method of claim 8, wherein etching the oxide layer is stopped on the intermediate layer.

10. The method of claim 1, before forming the oxide layer, further comprising forming a lining layer on the substrate, and forming the oxide layer on the lining layer.

11. The method of claim 10, wherein etching the oxide layer is stopped on the lining layer.

12. The method of claim 1, before forming the photoresist layer and after forming the oxide layer, further comprising forming an etching resistive layer on the oxide layer and forming a silicon-containing layer on the etching resistive layer, such that the photoresist layer is formed on the silicon-containing layer.

13. The method of claim 12, after removing the photoresist layer, further comprising removing the etching resistive layer and the silicon-containing layer.

14. A method of manufacturing an imprinting template using a semiconductor manufacturing process, comprising:

providing a substrate;

forming an oxide layer having a thickness in a range of 1000 angstroms to 8000 angstroms on the substrate;

forming a photoresist layer on the oxide layer;

performing a microlithography and etch process on the photoresist layer to form a pattern having a plurality of contact hole-like openings;

etching the oxide layer through the openings to form a plurality of pillar-shaped holes;

removing the photoresist layer;

filling a material layer into the pillar-shaped holes; and

partly removing the oxide layer to expose an upper part of the material layer to form a plurality of pillars, thereby forming an imprinting template.

15. The method of claim 14, wherein the pillars are regularly and periodically arranged in a pitch of micro dimension, sub-micro dimension, or nano dimension.

16. The method of claim 14, wherein the substrate comprises silicon.

17. The method of claim 14, wherein the oxide layer comprises silicon dioxide.

18. The method of claim 14, wherein the oxide layer is formed by a thermal oxidation process or a chemical vapor deposition process.

19. The method of claim 14, further comprising forming a cap layer over the oxide layer.

20. The method of claim 14, wherein etching the oxide layer is stopped on the surface of the substrate or further etching the substrate.

21. The method of claim 14, before forming the oxide layer, further comprising forming a lining layer on the substrate, and forming the oxide layer on the lining layer.

22. The method of claim 21, wherein etching the oxide layer is stopped on the lining layer.

23. The method of claim 14, wherein the step of forming the oxide layer is paused, an intermediate layer is further formed on the paused oxide layer, and the step of forming the oxide layer is continued on the intermediate layer.

24. The method of claim 23, wherein partly etching the oxide layer is to remove the portion of the oxide layer from the top till the intermediate layer.

25. The method of claim 14, before forming the photoresist layer and after forming the oxide layer, further comprising forming an etching resistive layer on the oxide layer and forming a silicon-containing layer on the etching resistive layer, such that the photoresist layer is formed on the silicon-containing layer.

26. The method of claim 25, after removing the photoresist layer, further comprising removing the etching resistive layer and the silicon-containing layer.

27. The method of claim 14, wherein the material layer comprises one selected from the group consisting of tungsten, copper, aluminum, an alloy thereof, and polysilicon.

28. The method of claim 27, wherein filling the material layer into the pillar-shaped holes comprising:

forming a barrier layer on the surface of the wall and the bottoms of the pillar-shaped holes;

depositing a material layer to fill up the pillar-shaped holes; and

performing a chemical mechanic polishing process to partly remove the material layer, thereby the height of the material layer is the same as the height of the oxide layer to expose the oxide layer.

29. The method of claim 14, wherein the pillars have a lower portion wider than an upper portion.

30. The method of claim 14, wherein the pillars have a bulged lower portion.

31. An imprinting template made by a semiconductor manufacturing process, comprising:

a substrate;

an oxide layer on the substrate, wherein the oxide layer has a thickness in a range of 1000 angstroms to 8000 angstroms and comprises a plurality of pillar-shaped holes.

32. The imprinting template of claim 31, wherein the substrate comprises silicon.

33. The imprinting template of claim 31, wherein the oxide layer comprises silicon dioxide.

34. The imprinting template of claim 31, wherein the pillar-shaped holes are regularly and periodically arranged in a pitch of micro dimension, sub-micro dimension, or nano dimension.

35. The imprinting template of claim 31, wherein the oxide layer is formed by a thermal oxidation process or a chemical vapor deposition process.

36. The imprinting template of claim 31, further comprising a cap layer on the top of the oxide layer.

37. The imprinting template of claim 31, further comprising an intermediate layer disposed in the oxide layer.

38. The imprinting template of claim 31, further comprising a lining layer underlying the oxide layer.

39. The imprinting template of claim 31, wherein the bottoms of the pillar-shaped holes are above the substrate or on the top surface of the substrate.

40. The imprinting template of claim 31, wherein the pillar-shaped holes penetrate through the oxide layer and into the substrate.

41. The imprinting template of claim 31, further comprising a releasing agent layer over the surface of the oxide layer.

42. An imprinting template made by a semiconductor manufacturing process, comprising:

a substrate;

an oxide layer on the substrate; and

a plurality of pillars penetrating the oxide layer and protruding the oxide layer.

43. The imprinting template of claim 42, wherein the substrate comprises silicon.

44. The imprinting template of claim 42, wherein the oxide layer comprises silicon dioxide.

45. The imprinting template of claim 42, wherein the pillars are regularly and periodically arranged in a pitch of micro dimension, sub-micro dimension, or nano dimension.

46. The imprinting template of claim 42, wherein the oxide layer is formed by a thermal oxidation process or a chemical vapor deposition process.

47. The imprinting template of claim 42, further comprising an etch stop layer on the top of the oxide layer.

48. The imprinting template of claim 42, further comprising a lining layer underlying the oxide layer.

49. The imprinting template of claim 42, wherein the bottoms of the pillars locates above the substrate or on the top surface of the substrate.

50. The imprinting template of claim 42, wherein the bottoms of the pillars locates in the substrate.

51. The imprinting template of claim 42, further comprising a releasing agent layer over the surface of the oxide layer.

52. A method of manufacturing an imprinting template using a semiconductor manufacturing process, comprising:

providing a silicon substrate;

forming a photoresist layer on the silicon substrate;

performing a microlithography and etch process on the photoresist layer to form a pattern having a plurality of contact hole-like openings;

etching the silicon substrate through the openings to form a plurality of pillar-shaped holes; and

removing the photoresist layer, thereby forming an imprinting template having a plurality of pillar-shaped holes.

53. A method of manufacturing an imprinting template using a semiconductor manufacturing process, comprising:

providing a silicon substrate;

forming a photoresist layer on the silicon substrate;

performing a microlithography and etch process on the photoresist layer to form a pattern having a plurality of contact hole-like openings;

etching the silicon substrate through the openings to form a plurality of pillar-shaped holes;

removing the photoresist layer;

filling a material layer into the pillar-shaped holes; and

partly removing the silicon substrate to expose an upper part of the material layer to form a plurality of pillars, thereby forming an imprinting template.

54. An imprinting template made by a semiconductor manufacturing process, comprising:

a silicon substrate comprising a plurality of pillar-shaped holes.

55. An imprinting template made by a semiconductor manufacturing process, comprising:

a silicon substrate; and

a plurality of pillars partly buried in and partly protruding the silicon substrate.