INTEGRATED SENSOR AND CIRCUITRY AND PROCESS THEREFOR

• US 20080188059A1
• Filed: 02/19/2008
• Published: 08/07/2008
• Est. Priority Date: 07/21/2005
• Status: Active Grant

• Current Assignee: Micro Inertial LLC
• Original Assignee: Evigia Systems, Inc.
• Inventors: Yazdi, Navid
• Granted Patent: US 7,732,302 B2
• Time in Patent Office: Days
• US Class Current: 438/456
• CPC Class Codes: B81B 2201/0235 Accelerometers
• CPC Class Codes: B81C 1/00253 Processes for integrating an electronic processing unit with a micromechanical structure not provided for in B81C1/0023 - B81C1/00246
• CPC Class Codes: B81C 2201/019 Bonding or gluing multiple substrate layers
• CPC Class Codes: G01C 19/5719 using planar vibrating masses driven in a translation vibration along an axis
• CPC Class Codes: G01P 1/023 for acceleration measuring devices
• CPC Class Codes: G01P 15/0802 Details
• CPC Class Codes: G01P 15/125 by capacitive pick-up
• CPC Class Codes: G01P 15/18 in two or more dimensions
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/16195 Flat cap [not enclosing an internal cavity]
• CPC Class Codes: H01L 2924/16235 Connecting to a semiconductor or solid-state bodies, i.e. cap-to-chip

Abstract

A micromachined sensor and a process for fabrication and vertical integration of a sensor and circuitry at wafer-level. The process entails processing a first wafer to incompletely define a sensing structure in a first surface thereof, processing a second wafer to define circuitry on a surface thereof, bonding the first and second wafers together, and then etching the first wafer to complete the sensing structure, including the release of a member relative to the second wafer. The first wafer is preferably a silicon-on-insulator (SOI) wafer, and the sensing structure preferably includes a member containing conductive and insulator layers of the SOI wafer. Sets of capacitively coupled elements are preferably formed from a first of the conductive layers to define a symmetric capacitive full-bridge structure.

Claims

1. A process of forming a micromachined sensor comprising a sensing structure and circuitry electrically coupled to the sensing structure, the process comprising:

processing a first wafer to incompletely define the sensing structure in a first surface thereof;

processing a second wafer to define the circuitry on a surface thereof;

bonding the first and second wafers together; and

then etching the first wafer to complete the sensing structure by removing portions of the first wafer at a second surface thereof opposite the first surface to define a member and by removing portions of the first wafer at the first surface thereof to release the member relative to the second wafer.

2. The process according to claim 1, wherein the member is a movable member that is released for movement relative to the second wafer as a result of the etching step.

3. The process according to claim 1, wherein the first wafer comprises a first conductive layer at the first surface thereof, a second conductive layer at the second surface thereof, and an insulator layer separating the first and second conductive layers.

4. The process according to claim 3, wherein the step of processing the first wafer comprises etching the first conductive layer, the member is formed from the second conductive layer as a result of the portions removed from the second surface of the first wafer being regions of the second conductive layer, and the member is released for movement relative to the second wafer as a result of the portions removed from the first surface of the first wafer being regions of the first conductive layer.

5. The process according to claim 1, wherein the step of processing the first wafer comprises:

forming in the first surface thereof at least first and second elements spaced apart to define a gap therebetween; and

forming in the first surface thereof means for supporting the member at oppositely-disposed ends thereof.

6. The process according to claim 5, wherein the bonding step comprises bonding the second element to the second wafer.

7. The process according to claim 6, wherein the etching step comprises entirely separating the second element from the remainder of the first wafer.

8. The process according to claim 5, wherein the bonding step comprises bonding a first portion of the supporting means to the second wafer.

9. The process according to claim 5, wherein the first and second elements and the support means are formed entirely in a first conductive layer at the first surface of the first wafer, and the member is formed in a second conductive layer at the second surface of the first wafer and separated from the first conductive layer by an insulator layer.

10. The process according to claim 1, wherein the first wafer comprises a first conductive layer at the first surface thereof, a second conductive layer at the second surface thereof, and an insulator layer separating the first and second conductive layers, the step of processing the first wafer comprising:

forming in the first conductive layer first and second sets of elements interdigitated with each other so that each element of the first set of elements is spaced apart from a corresponding element of the second set of elements to define a gap therebetween, a first group of the first set of elements being electrically isolated from a second group of the first set of elements by the insulator layer; and

forming in the first conductive layer means for supporting the member at oppositely-disposed ends thereof.

11. The process according to claim 10, wherein the bonding step comprises bonding the second set of elements to the second wafer.

12. The process according to claim 11, wherein the etching step comprises entirely separating the second set of elements from the insulator layer, while the first set of elements remain attached to the insulator layer.

13. The process according to claim 10, wherein the bonding step comprises bonding a first portion of the supporting means to the second wafer.

14. The process according to claim 10, wherein the first and second sets of elements and the support means are formed entirely in the first conductive layer, and the member is formed in the second conductive layer.

15. The process according to claim 10, wherein the step of processing the first wafer comprises forming at least one trench through the first conductive layer to electrically isolate a first group of the first set of elements from a second group of the first set of elements, the first group of the first set of elements being electrically connected to a first of the support means, the second group of the first set of elements being electrically connected to a second of the support means.

16. The process according to claim 1, wherein:

the step of processing the first wafer further comprises forming electrical contacts on the first surface thereof;

the step of processing the second wafer further comprises forming electrical contacts on the surface thereof; and

the electrical contacts are electrically connected following the bonding step.

17. The process according to claim 1, wherein the step of processing the first wafer further comprises defining a second sensing structure on the first wafer.

18. The process according to claim 1, further comprising the step of processing a third wafer to define a second sensing structure, and then bonding the third wafer to the first wafer following the etching step to define a multiple level sensor structure.