Thin film transistor and method of manufacturing the same

• US 20080203387A1
• Filed: 01/04/2008
• Published: 08/28/2008
• Est. Priority Date: 02/28/2007
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Song, I-hun, Park, Young-soo, Kang, Dong-hun, Kim, Chang-jung, Genrikh, Stefanovich
• Granted Patent: US 8,063,421 B2
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

Provided are a thin film transistor and a method of manufacturing the same. The thin film transistor may include a gate; a channel layer; a source and a drain, the source and the drain being formed of metal; and a metal oxide layer, the metal oxide layer being formed between the channel layer and the source and the drain. The metal oxide layer may have a gradually changing metal content between the channel layer and the source and the drain.

Claims

1. A thin film transistor (TFT) including:

a gate;

a channel layer;

a source and a drain, the source and the drain being formed of metal; and

a metal oxide layer, the metal oxide layer being formed between the channel layer and the source and the drain.

2. The TFT of claim 1, wherein the metal oxide layer has a gradually changing metal content between the channel layer and the source and the drain.

3. The TFT of claim 2, wherein the metal content in the metal oxide layer is gradually increased or decreased in a direction toward the channel layer.

4. The TFT of claim 1, wherein the metal oxide layer is a stoichiometric or non-stoichiometric layer.

5. The TFT of claim 1, wherein the metal oxide layer includes a transition metal having an oxidation characteristic higher than or similar to that of ZnO.

6. The TFT of claim 1, wherein the source and the drain are double-layers formed of metal.

7. The TFT of claim 1, wherein the channel layer is an oxide semiconductor layer.

8. The TFT of claim 1, wherein the metal contained in the metal oxide layer is the same as the metal of the source and the drain.

9. The TFT of claim 1, wherein the gate is formed above or under the channel layer or buried in the channel layer.

10. The TFT of claim 5, wherein the transition metal is one selected from the group consisting of Ti, Mo, Cr or W.

11. The TFT of claim 1, wherein the source and the drain are formed of at least one selected from the group consisting of Ti, Mo, Cr, W, Zr, Hf, Nb, Ta, Ag, Au, Al, Cu, Co, Sb, V, Ru, Pt, Pd, Zn, and Mg.

12. The TFT of claim 7, wherein the oxide semiconductor layer is an a(In₂O₃).b(Ga₂O₃).c(ZnO) or a(In2O3).b(ZnO).c(SnO) (where a, b, and c are integers satisfying a≧

0, b≧

0, and c>

0, respectively).

13. A method of manufacturing a thin film transistor (TFT) comprising:

forming a gate on a substrate;

forming a gate insulating layer covering the gate on the substrate;

forming a channel layer on the gate insulating layer; and

forming a source and a drain by sequentially stacking a metal oxide layer and a metal layer on the channel layer and the gate insulating layer.

14. The method of claim 13, wherein the metal oxide layer includes a transition metal having a high oxidation or similar characteristic than ZnO.

15. The method of claim 14, wherein the transition metal is one selected from the group consisting of Al, Ti, Mo, Cr or W.

16. The method of claim 13, wherein after forming the metal oxide layer and the metal layer, annealing a resultant structure is performed.

17. The method of claim 16, wherein the annealing is performed between 250°

C.˜

450°

C. in a nitrogen atmosphere using a furnace, a rapid thermal annealing (RTA), or laser.

18. The method of claim 13, wherein the metal layer is a double-layer.

19. The method of claim 13, wherein the metal layer is formed of at least one selected from the group consisting of Ti, Mo, Cr, W, Zr, Hf, Nb, Ta, Ag, Au, Al, Cu, Co, Sb, V, Ru, Pt, Pd, Zn, and Mg.

31. The method of claim 13, wherein the channel layer is first formed on the substrate;

the source and the drain are formed by sequentially stacking the metal oxide layer and the metal layer on the channel layer and the substrate; and

the gate and the gate insulating layer are formed after forming the source and the drain by forming the gate insulating layer to cover the channel layer, the metal oxide layer, and the metal layer, and forming the gate on the gate insulating layer.

20. A method of manufacturing a thin film transistor (TFT) comprising

forming a gate on a substrate;

forming a gate insulating layer covering the gate on the substrate;

forming a channel layer on the gate insulating layer;

stacking a metal layer on the channel layer and the gate insulating layer; and

forming a metal oxide layer between the metal layer and the channel layer.

21. The method of claim 20, wherein the metal oxide layer is formed by annealing a resultant structure including the metal layer.

22. The method of claim 21, wherein the annealing is performed using a furnace, rapid thermal annealing (RTA), or a laser.

23. The method of claim 22, wherein the annealing is performed between 250°

C.˜

450°

C. in an atmosphere containing nitrogen or oxygen.

24. The method of claim 22, wherein the annealing is performed in an oxygen atmosphere between 250°

C.˜

45°

C.

25. The method of claim 20, wherein the channel layer is an oxide semiconductor layer.

26. The method of claim 25, wherein the oxide semiconductor layer is a(In₂O₃).b(Ga₂O₃).c(ZnO), where a, b, and c are integers satisfying a≧

0, b≧

0, and c>

0.

27. The method of claim 20, wherein the metal oxide layer includes a transition metal having a higher oxidation characteristic than ZnO.

28. The method of claim 27, wherein the transition metal is one selected from the group consisting of Ti, Mo, Cr or W.

29. The method of claim 20, wherein the metal layer is a double-layer.

30. The method of claim 20, wherein the metal layer is formed of at least one selected from the group consisting of Ti, Mo, Cr, W, Zr, Hf, Nb, Ta, Ag, Au, Al, Cu, Co, Sb, V, Ru, Pt, Pd, Zn, and Mg.

32. The method of claim 20, wherein the channel layer is first formed on the substrate;

the metal layer is formed on the channel layer and the substrate;

the gate insulating layer is formed to cover the metal layer and the channel layer; and

the metal oxide layer is formed after forming the gate on the gate insulating layer.

33. The method of claim 20, wherein the channel layer is first formed on the substrate;

the metal layer is formed on the channel layer and the substrate;

then the metal oxide layer is formed;

the gate insulating layer is formed to cover the metal layer, the metal oxide layer, and the channel layer; and

the gate is formed on the gate insulating layer.

34. The method of claim 23, wherein the channel layer is an oxide semiconductor layer.

35. The method of claim 24, wherein the channel layer is an oxide semiconductor layer.

36. The method of claim 34, wherein the oxide semiconductor layer is a(In₂O₃).b(Ga₂O₃).c(ZnO) or a(In2O3) b(ZnO).c(SnO), where a, b, and c are integers satisfying a≧

0, b≧

0, and c>

0.

37. The method of claim 35, wherein the oxide semiconductor layer is a(In₂O₃).b(Ga₂O₃).c(ZnO) or a(In2O3) b(ZnO).c(SnO), where a, b, and c are integers satisfying a≧

0, b≧

0, and c>

0.

38. The method of claim 29, wherein the metal layer is formed of at least one selected from the group consisting of Ti, Mo, Cr, W, Zr, Hf, Nb, Ta, Ag, Au, Al, Cu, Co, Sb, V, Ru, Pt, Pd, Zn, and Mg.