Memory Element and Semiconductor Device, and Method for Manufacturing the Same

• US 20080205132A1
• Filed: 02/20/2008
• Published: 08/28/2008
• Est. Priority Date: 02/26/2007
• Status: Active Grant

• Current Assignee: Oracle International Corporation (Oracle Corporation)
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Hirakata, Yoshiharu
• Granted Patent: US 8,283,724 B2
• Time in Patent Office: Days
• US Class Current: 365/182
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: G11C 13/0002 using resistive RAM [RRAM] elements
• CPC Class Codes: G11C 13/0014 comprising cells based on organic memory material
• CPC Class Codes: G11C 2213/77 Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor
• CPC Class Codes: H01L 23/5252 comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
• CPC Class Codes: H01L 27/101 including resistors or capacitors only
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 20/00 Read-only memory [ROM] devices
• CPC Class Codes: H10B 20/20 Programmable ROM [PROM] devices comprising field-effect components H10B20/10 takes precedence
• CPC Class Codes: H10N 70/021 Formation of the switching material, e.g. layer deposition

Abstract

It is an object to solve inhibition of miniaturization of an element and complexity of a manufacturing process thereof. It is another object to provide a nonvolatile memory device and a semiconductor device having the memory device, in which data can be additionally written at a time besides the manufacturing time and in which forgery caused by rewriting of data can be prevented. It is further another object to provide an inexpensive nonvolatile memory device and semiconductor device. A memory element is manufactured in which a first conductive layer, a second conductive layer that is beside the first conductive layer, and conductive fine particles of each surface which is covered with an organic film are deposited over an insulating film. The conductive fine particles are deposited between the first conductive layer and the second conductive layer.

Claims

1. A memory element comprising:

a first conductive layer formed over a first region of an insulating surface;

a second conductive layer formed over a second region of the insulating surface; and

a conductive particle deposited between the first conductive layer and the second conductive layer, the conductive particle having a surface covered with an organic film,

wherein the first region is apart from the second region, and

wherein the first and second conductive layers are electrically connectable to each other at least through the conductive particle as a result in a writing operation of the memory element.

2. A memory element according to claim 1,

wherein the first conductive layer and the second conductive layer are in direct contact with the insulating surface.

3. A memory element according to claim 1, further comprising an insulating film between the insulating surface and the second conductive layer while the first conductive layer is in direct contact with the insulating surface.

4. A memory element according to claim 1, further comprising

at least one conductive particle between a side face of the first conductive layer and a side face of the second conductive layer which is opposite to the side face.

5. A memory element according to claim 1,

wherein the side face of the first conductive layer and the side face of the second conductive layer which is opposite to the side face have a tapered shape.

6. A memory element according to claim 1,

wherein the conductive particle is a conductive fine particle having a grain size of 5 to 30 nm.

7. A memory element according to claim 1,

wherein the first conductive layer is a bit line, and the second conductive layer is a word line.

8. A memory element according to claim 1,

wherein the first conductive layer is a word line, and the second conductive layer is a bit line.

9. A memory element comprising:

a first conductive layer formed over an insulating surface;

an insulating film formed over the insulating surface and over a part of the first conductive layer to expose a portion of the first conductive layer;

a second conductive layer formed over the insulating film wherein the second conductive layer partly overlaps the first conductive layer with the insulating film interposed therebetween; and

a conductive particle deposited on the exposed portion of the first conductive layer,

wherein the first and second conductive layers are electrically connectable to each other at least through the conductive particle as a result in a writing operation of the memory element.

10. A memory element according to claim 9,

wherein the conductive particle is a conductive fine particle having a grain size of 5 to 30 nm.

11. A memory element according to claim 9,

wherein the first conductive layer is a bit line, and the second conductive layer is a word line.

12. A memory element according to claim 9,

wherein the first conductive layer is a word line, and the second conductive layer is a bit line

13. A semiconductor device including a plurality of memory elements each of which comprises:

a first conductive layer and a second conductive layer that is beside the first conductive layer with an interval “

d”

over a same insulating film;

a first conductive fine particle that overlaps the first conductive layer,

a second conductive fine particle that overlaps a region between the first conductive layer and the second conductive layer; and

a third conductive fine particle that overlaps the second conductive layer.

14. A semiconductor device according to claim 13,

wherein the interval “

d”

between the first conductive layer and the second conductive layer is smaller than a grain size of the second conductive fine particle.

15. A semiconductor device according to claim 13,

wherein a surface of the second conductive fine particle is covered with an organic film.

16. A semiconductor device according to claim 13,

wherein the first conductive layer is a bit line, and the second conductive layer is a word line.

17. A semiconductor device according to claim 13,

wherein the first conductive layer is a word line, and the second conductive layer is a bit line.

18. A semiconductor device according to claim 13,

wherein a thin film transistor is provided, and

wherein the thin film transistor is electrically connected to the first conductive layer or the second conductive layer.

19. A semiconductor device according to claim 13,

wherein an antenna and a power supply generating circuit are provided.

20. A method for manufacturing a semiconductor device, comprising the steps of:

forming a conductive film over an insulating surface;

forming a mask over the conductive film;

performing etching selectively to the conductive film using the mask to form a first conductive layer and a second conductive layer; and

forming a layer containing a conductive fine particle at least between a side face of the first conductive layer and a side face of the second conductive layer which is opposite to the side face.

21. A method for manufacturing a semiconductor device according to claim 20,

wherein a surface of the conductive fine particle is covered with an organic film.

22. A method for manufacturing a semiconductor device according to claim 20,

wherein the step for forming a mask is conducted by a nanoimprint method.

23. A method for manufacturing a semiconductor device according to claim 20,

wherein the step for forming a layer containing a conductive fine particle is conducted by a droplet discharge method.