Radio frequency isolation for SOI transistors

• US 20080217727A1
• Filed: 01/16/2008
• Published: 09/11/2008
• Est. Priority Date: 03/11/2007
• Status: Abandoned Application

• Current Assignee: Skyworks Solutions Incorporated
• Original Assignee: Skyworks Solutions Incorporated
• Inventors: Kjar, Raymond A.
• Application Number:
  US12/009,071
• Publication Number:
  US 20080217727A1
• Time in Patent Office: Days
• US Class Current: 257/499
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/76264 SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
• CPC Class Codes: H01L 21/765 by field effect H01L21/76264 takes precedence
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/7394 on an insulating layer or substrate, e.g. thin film device or device isolated from the bulk substrate H01L29/7398 takes precedence
• CPC Class Codes: H01L 29/78606 with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 29/78609 for preventing leakage current H01L29/78618 takes precedence

Abstract

According to an exemplary embodiment, a structure includes at least one SOI (semiconductor-on-insulator) transistor situated over a buried oxide layer, where the buried oxide layer overlies a bulk substrate. The structure further includes an electrically charged field control ring situated over the buried oxide layer and surrounding the at least one SOI transistor. A width of the electrically charged field control ring is greater than a thickness of the buried oxide layer. The electrically charged field control ring reduces a conductivity of a surface portion of the bulk substrate underlying the field control ring, thereby minimizing RF coupling of the at least one SOI transistor through the bulk substrate. The structure further includes an isolation region situated between the electrically charged field control ring and the at least one SOI transistor. A method to achieve and implement the disclosed structure is also provided.

Claims

1. A structure comprising:

at least one SOI (semiconductor-on-insulator) transistor situated over a buried oxide layer, said buried oxide layer overlying a bulk substrate;

an electrically charged field control ring situated over said buried oxide layer and surrounding said at least one SOI transistor;

wherein said electrically charged field control ring reduces a conductivity of a surface portion of said bulk substrate underlying said field control ring, thereby minimizing RF coupling of said at least one SOI transistor through said bulk substrate.

2. The structure of claim 1 further comprising an isolation region situated between said electrically charged field control ring and said at least one SOI transistor.

3. The structure of claim 1, wherein said electrically charged field control ring is doped with a dopant having a same conductivity type as said bulk substrate.

4. The structure of claim 1, wherein a width of said electrically charged field control ring is greater than a thickness of said buried oxide layer.

6. The structure of claim 1, wherein said electrically charged field control ring is coupled to a bias voltage.

7. The structure of claim 1, wherein said electrically charged field control ring comprises silicon.

8. The structure of claim 1, wherein said electrically charged field control ring comprises a metal.

9. The structure of claim 1, wherein said electrically charged field control ring comprises a high resistivity conductive material.

5. The structure of claim 5, wherein said width of said electrically charged field control ring is greater than said thickness of said buried oxide layer by a factor of between 3.0 and 10.0.

10. A structure comprising:

a plurality of SOI (semiconductor-on-insulator) transistors situated over a buried oxide, said buried oxide layer overlying a bulk substrate, said plurality of SOI transistors being coupled in series;

an electrically charged field control ring situated over said buried oxide layer and surrounding said plurality of SOI transistors;

wherein said electrically charged field control ring reduces a conductivity of a surface portion of said bulk substrate underlying said field control ring, thereby minimizing RF coupling of said plurality of SOI transistors through said bulk substrate.

11. The structure of claim 10 further comprising an isolation region situated between said electrically charged field control ring and said plurality of SOI transistors.

12. The structure of claim 10, wherein said electrically charged field control ring is doped with a dopant having a same conductivity type as said bulk substrate.

13. The structure of claim 10, wherein a width of said electrically charged field control ring is greater than a thickness of said buried oxide layer.

14. The structure of claim 10, wherein said electrically charged field control ring is coupled to a bias voltage.

15. The structure of claim 10, wherein said electrically charged field control ring comprises a conductive material selected from the group consisting of silicon and a metal.

16. The structure of claim 10, wherein said plurality of SOI transistors form an RF switch.

17. A method for minimizing RF coupling of at least one SOI transistor through a bulk substrate of an SOI substrate, said method comprising steps of:

forming a field control ring in said SOI substrate, said field control ring surrounding said at least one SOI transistor;

electrically charging said field control ring;

wherein said field control ring reduces a conductivity of a surface portion of said bulk substrate underlying said field control ring, thereby minimizing RF coupling of said at least one SOI transistor through said bulk substrate.

18. The method of claim 17, wherein said step of electrically charging said field control ring comprises implanting a dopant in said field control ring.

19. The method of claim 17, wherein said step of electrically charging said field control ring comprises coupling a bias voltage to said field control ring.

20. The method of claim 17, wherein said field control ring comprises a conductive material selected from the group consisting of silicon, polysilicon, and a metal.

21. The method of claim 17, wherein a width of said field control ring is greater than a thickness of a buried oxide layer situated over said bulk substrate.