Advanced Repeater Utilizing Signal Distribution Delay

• US 20080218215A1
• Filed: 05/20/2008
• Published: 09/11/2008
• Est. Priority Date: 06/08/2004
• Status: Active Grant

• Current Assignee: Intellectual Ventures Funding LLC (Intellectual Ventures LLC)
• Original Assignee: Transmeta Corporation (Novafora, Inc.)
• Inventors: Pitkethly, Scott, Masleid, Robert Paul
• Granted Patent: US 7,768,295 B2
• Time in Patent Office: Days
• US Class Current: 326/86
• CPC Class Codes: H03K 19/01721 by means of a pull-up or down element

Abstract

An advanced repeater utilizing signal distribution delay. In accordance with a first embodiment of the present invention, such an advanced repeater circuit comprises an output stage for driving an output signal line responsive to an input signal and a feedback loop coupled to said output signal line for changing state of said output stage subsequent to a delay after a transition of said output signal. The delay is due to transmission line effects of said output signal line.

Claims

1. A circuit comprising:

a drive circuit for selective driving an output node high and low;

an OR gate having an output coupled to the drive circuit and a first input coupled to an input node;

an AND gate having an output coupled to the drive circuit and a first input coupled to the input node; and

a feedback loop coupled between the output node and second inputs of the OR gate and the AND gate.

2. The circuit of claim 1, wherein the drive circuit comprises a p-type transistor and an n-type transistor, wherein the gate of the p-type transistor is coupled to the output of the OR gate and the gate of the n-type transistor is coupled to the output of the AND gate.

3. The circuit of claim 1, wherein the OR gate comprises a NOR gate and an inverter.

4. The circuit of claim 1, wherein the AND gate comprises a NAND gate and an inverter.

5. The circuit of claim 1, wherein the feedback loop comprises a transmission line effect feedback loop.

6. The circuit of claim 1, wherein the feedback loop comprises a clock signal distribution network or tree.

7. The circuit of claim 1, wherein the feedback loop introduces a delay between the output node and the second inputs of the OR gate and the AND gate.

8. The circuit of claim 7, wherein the delay is sufficient for the drive circuit to drive the output node to a predetermined level.

9. The circuit of claim 1, further comprising a keeper circuit coupled to the output node.

10. A repeater circuit comprising:

a driver circuit having an output coupled to an output node;

a feedback loop, coupled between the output node and a first input of a control circuit, and for introducing a delay between the output node and the first input of the control circuit; and

the control circuit, having an output coupled to an input of the driver circuit and a second input coupled to an input node, and for causing the driver circuit to drive an output signal at the output node to a given state in response to a transition of an input signal at the input node and ceasing driving the output signal after the delay in response to a transition of the output signal.

11. The repeater circuit of claim 10, wherein the driver circuit comprises:

a first transistor for driving the output node high; and

a second transistor for driving the output node low.

12. The repeater circuit of claim 11, wherein the control circuit comprises:

an OR gate, for controlling the first transistor, having a first input coupled to an input node and a second input coupled to the feedback loop; and

an AND gate, for controlling the second transistor, having a first input coupled to the input node and a second input coupled to the feedback loop.

13. The repeater circuit of claim 10, wherein the feedback loop comprises a transmission line effect feedback loop.

14. The repeater circuit of claim 10, wherein the feedback loop comprises a clock signal distribution network or tree.

15. The repeater circuit of claim 10, further comprising a keeper circuit coupled to the output node for weakly holding the output signal in its present state.

16. The repeater circuit of claim 10, wherein the output signal is inverted relative to the input signal.

17. The repeater circuit of claim 10, wherein the delay is long enough to drive the output signal to a given level and short enough not to resist a next transition of the output signal.

18. The repeater circuit of claim 10, wherein the delay is short enough that the driver circuit stops driving the output signal prior to a next transition of the input signal.