APPARATUS AND METHOD FOR INTEGRATING NONVOLATILE MEMORY CAPABILITY WITHIN SRAM DEVICES

• US 20080225590A1
• Filed: 03/12/2007
• Published: 09/18/2008
• Est. Priority Date: 03/12/2007
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: International Business Machines Corporation
• Inventors: Lamorey, Mark C. H.
• Granted Patent: US 7,692,954 B2
• Time in Patent Office: Days
• US Class Current: 365/185.05
• CPC Class Codes: G11C 11/16 using elements in which the storage effect is based on magnetic spin effect
• CPC Class Codes: G11C 14/0081 and the nonvolatile element is a magnetic RAM [MRAM] element or ferromagnetic cell

Abstract

A nonvolatile static random access memory (SRAM) device includes a pair of cross-coupled, complementary metal oxide semiconductor (CMOS) inverters configured as a storage cell for a bit of data and a pair of magnetic spin transfer devices coupled to opposing sides of the storage cell. The magnetic spin transfer devices are configured to retain the storage cell data therein following removal of power to the SRAM device, and are further configured to initialize the storage cell with the retained data upon application of power to the SRAM device.

Claims

1. A nonvolatile static random access memory (SRAM) device, comprising:

a pair of cross-coupled, complementary metal oxide semiconductor (CMOS) inverters configured as a storage cell for a bit of data; and

a pair of magnetic spin transfer devices coupled to opposing sides of the storage cell;

wherein the magnetic spin transfer devices are configured to retain the storage cell data therein following removal of power to the SRAM device, and are further configured to initialize the storage cell with the retained data upon application of power to the SRAM device.

2. The device of claim 1, wherein the magnetic spin transfer devices are configured to retain storage cell data by programming of a low resistance state in one of the spin transfer devices and a high resistance state in the other of the spin transfer devices.

3. The device of claim 2, wherein the magnetic spin transfer devices are programmed to the low and high resistance states by application of current therethrough.

4. The device of claim 3, wherein the low resistance state corresponds to current passed through either of the magnetic spin transfer devices in a first direction, and the high resistance state corresponds to current passed through either of the magnetic spin transfer devices in a second, opposite direction.

5. The device of claim 3, further comprising a common programming node coupled to the pair of magnetic spin transfer devices, the common programming node configured to implement programming of the magnetic spin transfer devices for storage cell data retention, and initialization of the storage cell with the retained data in the magnetic spin transfer devices.

6. The device of claim 5, wherein the programming node is charged to a first bias voltage during a store operation of the SRAM cell, the first bias voltage configured to induce an outward flow of current from the side of the SRAM cell having a logical high voltage stored thereon, and to induce an inward flow of current into the SRAM call having a logical low voltage stored thereon.

7. The device of claim 6, wherein the first bias voltage is about half the value of the logical high voltage.

8. The device of claim 6, wherein the programming node is charged to a second bias voltage during a restore operation of the SRAM cell, the second bias voltage configured to induce a current flow through the SRAM cell, wherein the state of the cell is initialized in a manner such that the cell node corresponding to the spin transfer device programmed at the low resistance state assumes the second bias voltage.

9. The device of claim 8, wherein the second bias voltage is the logic low voltage.

10. The device of claim 9, wherein the second bias voltage is the logic high voltage.

11. The device of claim 8, further comprising a first port and a second port each coupled to the SRAM cell, wherein:

the first port comprises a first pair of pass gates and a first pair of bitlines, the first pair of bitlines configured for read and write operations of the SRAM cell during power on conditions; and

the second port comprises a second pair of pass gates, a second pair of bitlines and the pair of spin transfer devices.

12. The device of claim 8, further comprising a first port and a second port each coupled to the SRAM cell, wherein:

the first port comprises a first pair of pass gates and a first pair of bitlines, the first pair of bitlines configured for read and write operations of the SRAM cell during power on conditions; and

the second port comprises a second pair of pass gates, the pair of spin transfer devices, and a common node connected to the pair of spin transfer devices, wherein the programming node corresponds to the common node.

13. The device of claim 8, further comprising:

a single port coupled to the SRAM cell, the single port comprising a pair of pass gates, the pair of spin transfer devices and a pair of bitlines;

wherein the pair of bitlines is configured for read and write operations of the SRAM cell during power on conditions, and wherein the pair of bitlines also serves as the programming node.

14. A method of integrating nonvolatile capability within a static random access memory (SRAM) device, the method comprising:

coupling a pair of magnetic spin transfer devices to opposing sides of an SRAM storage cell; and

the SRAM storage cell further comprising a pair of cross-coupled, complementary metal oxide semiconductor (CMOS) inverters configured to store a bit of data therein,

wherein the magnetic spin transfer devices are configured to retain the storage cell data therein following removal of power to the SRAM device, and are further configured to initialize the storage cell with the retained data upon application of power to the SRAM device.

15. The method of claim 14, wherein the magnetic spin transfer devices are configured to retain storage cell data by programming of a low resistance state in one of the spin transfer devices and a high resistance state in the other of the spin transfer devices.

16. The method of claim 15, wherein the magnetic spin transfer devices are programmed to the low and high resistance states by application of current therethrough.

17. The method of claim 16, wherein the low resistance state corresponds to current passed through either of the magnetic spin transfer devices in a first direction, and the high resistance state corresponds to current passed through either of the magnetic spin transfer devices in a second, opposite direction.

18. The method of claim 16, further comprising coupling a common programming node to the pair of magnetic spin transfer devices, the common programming node configured to implement programming of the magnetic spin transfer devices for storage cell data retention, and initialization of the storage cell with the retained data in the magnetic spin transfer devices.

19. The method of claim 18, wherein the programming node is charged to a first bias voltage during a store operation of the SRAM cell, the first bias voltage configured to induce an outward flow of current from the side of the SRAM cell having a logical high voltage stored thereon, and to induce an inward flow of current into the SRAM call having a logical low voltage stored thereon.

20. The method of claim 19, wherein the first bias voltage is about half the value of the logical high voltage.

21. The method of claim 19, wherein the programming node is charged to a second bias voltage during a restore operation of the SRAM cell, the second bias voltage configured to induce a current flow through the SRAM cell, wherein the state of the cell is initialized in a manner such that the cell node corresponding to the spin transfer device programmed at the low resistance state assumes the second bias voltage.

22. The method of claim 21, wherein the second bias voltage is the logic low voltage.

23. The method of claim 22, wherein the second bias voltage is the logic high voltage.

24. The method of claim 21, further comprising coupling a first port and a second port to the SRAM cell, wherein:

the first port comprises a first pair of pass gates and a first pair of bitlines, the first pair of bitlines configured for read and write operations of the SRAM cell during power on conditions; and

the second port comprises a second pair of pass gates, a second pair of bitlines and the pair of spin transfer devices.

25. The method of claim 21, further comprising coupling a first port and a second port to the SRAM cell, wherein:

the first port comprises a first pair of pass gates and a first pair of bitlines, the first pair of bitlines configured for read and write operations of the SRAM cell during power on conditions; and

the second port comprises a second pair of pass gates, the pair of spin transfer devices, and a common node connected to the pair of spin transfer devices, wherein the programming node corresponds to the common node.

26. The method of claim 21, further comprising:

coupling a single port to the SRAM cell, the single port comprising a pair of pass gates, the pair of spin transfer devices and a pair of bitlines,

wherein the pair of bitlines is configured for read and write operations of the SRAM cell during power on conditions, and wherein the pair of bitlines also serves as the programming node.

27. A method for implementing nonvolatile retention of a data bit stored in an SRAM cell, the method comprising:

charging a programming node to a first bias voltage about halfway between a logic high voltage and a logic low voltage of the SRAM cell;

respectively coupling one side of a pair of magnetic spin transfer devices to opposing sides of an SRAM storage cell through activation of a pair of pass gate devices, with an opposite side of the pair of magnetic spin transfer devices coupled to the programming node, so as to pass current through a first of the magnetic spin transfer devices in a first direction, and to pass through a second of the magnetic spin transfer device in a second, opposite direction,

wherein passing current in the first direction causes programming of the first magnetic spin transfer device to a low resistance state, and passing current in the second direction causes programming of the second spin transfer device to a high resistance state; and

removing a source of power to the SRAM cell upon achieving the low resistance state in the first magnetic spin transfer device, and achieving the high resistance state in the second magnetic spin transfer device;

wherein the data stored in the SRAM cell prior to power source removal is maintained within the pair of magnetic spin transfer devices following power source removal.

28. The method of claim 27, wherein the logic state of the SRAM cell is maintained during programming of the pair of magnetic spin transfer devices.

29. The method of claim 27, further comprising initializing the SRAM cell in a data restore operation during power up, wherein cell data maintained within the pair of magnetic spin transfer devices is restored to the SRAM cell.

30. The method of claim 29, wherein the restore operation further comprises:

applying a source of power to the SRAM cell;

charging the programming node to a second bias voltage, and coupling the pair of magnetic spin transfer devices to the SRAM cell, the second bias voltage configured to induce a current flow through the SRAM cell, wherein the state of the cell is initialized in a manner such that the cell node corresponding to the first spin transfer device programmed at the low resistance state assumes the second bias voltage.

31. The method of claim 30, wherein the second bias voltage is the logic low voltage.

32. The method of claim 30, wherein the second bias voltage is the logic high voltage.

33. The method of claim 30, wherein the programming node comprises an electrically separate path with respect to a pair of bitlines used for read and write operations of the SRAM cell.

34. The method of claim 30, wherein the programming node comprises a pair of bitlines used for read and write operations of the SRAM cell.

35. The method of claim 30, further comprising activating the pass gates during power up so as to prevent stray current flowing through the pair of magnetic spin transfer devices.