Circuit

• US 20080225603A1
• Filed: 03/21/2007
• Published: 09/18/2008
• Est. Priority Date: 03/15/2007
• Status: Active Grant

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Qimonda AG (Infineon Technologies AG)
• Inventors: Hein, Thomas
• Granted Patent: US 8,207,976 B2
• Time in Patent Office: Days
• US Class Current: 365/189.05
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1066 Output synchronization
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1093 Input synchronization

Abstract

An embodiment of a circuit includes an output buffer, a data interface which is at least in a position to transmit data, the data interface being coupled to an output of the output buffer, a command/address interface coupled to an input of the output buffer, a memory core coupled to the input of the output buffer, and a controller circuit configured to cause data stored within the output buffer to be output to the data interface, further configured to cause data stored within the memory core to be output to the input of the output buffer, so that the data is stored within the output buffer, and further configured to cause provision of data received at the command/address interface to the input of the output buffer, so that the data is stored within the output buffer.

Claims

1. A circuit comprising:

an output buffer comprising an input and an output;

a data interface which is at least in a position to transmit data, the data interface being coupled to the output of the output buffer;

a command/address interface coupled to the input of the output buffer;

a memory core coupled to the input of the output buffer; and

a controller circuit adapted to cause data stored within the output buffer to be output to the data interface upon reception of a first signal, further adapted to cause data stored within the memory core to be output to the input of the output buffer upon reception of a second signal, so that the data is stored within the output buffer, and further adapted to cause provision of data received at the command/address interface to the input of the output buffer upon reception of a third signal, so that the data is stored within the output buffer.

2. The circuit as claimed in claim 1, further comprising a temporary memory coupled between the command/address interface and the output buffer and adapted to allow temporary storage of the data received at the command/address interface.

3. The circuit as claimed in claim 2, further comprising a bus with at least one signal line between the memory core and the input of the output buffer, the temporary memory being part of the bus, and the bus comprising a memory element for each of the at least one signal line.

4. The circuit as claimed in claim 3, further comprising a demultiplexer connected between the bus and the command/address interface and adapted to couple data which is received at the command/address interface into the bus as a function of an addressing signal.

5. The circuit as claimed in claim 2, wherein the memory circuit is adapted to allow the temporary memory to be addressed via signal lines of the command/address interface.

6. The circuit as claimed in claim 1, wherein the output buffer is adapted to simultaneously buffer a larger amount of data than is simultaneously receivable via the command/address interface.

7. The circuit as claimed in claim 1, wherein the output buffer is adapted to simultaneously store 72 bits or 80 bits, and the command/address interface is adapted to simultaneously receive 9 bits or 10 bits.

8. The circuit as claimed in claim 1, further comprising a processing circuit and a second output buffer comprising an input and an output, the processing circuit being coupled to the input of the second output buffer, the output of the second output buffer being coupled to the data interface or a further pin, and the controller circuit being adapted to cause data which is stored within the second output buffer to be output to the data interface or the further pin, the controller circuit further being adapted to cause data which is provided by the processing circuit to be stored within the second output buffer, and the controller circuit further being adapted to cause data which is received at the command/address interface to be stored within the second output buffer.

9. The circuit as claimed in claim 8, further comprising a second temporary memory connected between the command/address interface and the input of the second output buffer, and adapted to enable temporary storage of at least part of the data coming in at the command/address interface.

10. The circuit as claimed in claim 9, wherein the processing circuit is coupled to the input of the second output buffer via a second bus, wherein the second data bus comprises at least one signal line, the second bus comprising the second temporary memory, and each signal line of the at least one signal line of the second bus comprising a memory element as the second temporary memory.

11. The circuit as claimed in claim 10, further comprising a second demultiplexer coupled between the second bus and the command/address interface, and adapted to couple the data which is received at the command/address interface into the bus as a function of the addressing signal or of a further addressing signal.

12. The circuit as claimed in claim 9, wherein the memory circuit is adapted to enable the first or second temporary memory to be addressed via signal lines of the command/address interface.

13. The circuit as claimed in claim 8, wherein the second output buffer is adapted to buffer a larger amount of data than may be provided at the same time to the second output buffer via the command/address interface.

14. The circuit as claimed in claim 8, wherein the second output buffer is adapted to buffer 8 bits in each case, and the memory circuit further being adapted to provide less than 8 bits to the second output buffer at any one time.

15. The circuit as claimed in claim 8, wherein the processing circuit is an EDC circuit adapted to calculate a check sum on the basis of data provided to the processing circuit.

16. The circuit as claimed in claim 1, wherein the memory circuit comprises a plurality of output buffers which are each coupled to the memory core via an input, which are each coupled to the data interface via an output, and which are each coupled to the command/address interface via their inputs, the memory circuit being adapted to cause the data which is received at the command/address interface to be stored within each of the output buffers of the plurality of output buffers.

17. The circuit as claimed in claim 1, wherein the memory circuit is a GDDRx memory circuit, x designating a GDDR standard.

18. The circuit as claimed in claim 1, wherein the memory circuit is a DRAM memory circuit.

19. A circuit comprising:

an output buffer comprising an input and an output;

a data interface adapted to allow at least the transmission of data, the data interface being coupled to the output of the output buffer;

a command/address interface;

a memory core;

a bus coupling the memory core to the input of the output buffer, the bus comprising a plurality of signal lines, each of the signal lines of the plurality of signal lines of the bus comprising a memory element;

a demultiplexer coupling the command/address interface to the bus such that data received at the command/address interface may be coupled into the bus as a function of an addressing signal; and

a controller circuit adapted to cause data stored within the output buffer to be output to the data interface upon reception of a signal, further adapted to cause data stored within the memory core to be output to the input of the output buffer upon reception of a second signal, so that the data is stored within the output buffer, and further adapted to cause provision of data received at the command/address interface to the input of the output buffer upon reception of a third signal, so that the data is stored within the output buffer,

the memory circuit being adapted to receive the address signal via signal lines of the command/address interface.

20. The circuit as claimed in claim 19, further comprising:

an EDC circuit;

a second output buffer comprising an input and an output;

a second bus comprising a plurality of signal lines, each signal line of the plurality of signal lines comprising a memory circuit, the plurality of the memory elements forming a temporary memory which may be addressed via the addressing signal or a further addressing signal, and the second bus coupling the EDC circuit to the input of the second output buffer; and

a demultiplexer coupling the command/address interface to the second bus such that at least part of the data received at the command/address interface may be coupled into the second bus on the basis of the address signal or the further address signal,

the output of the second output buffer being coupled to the data interface or to a further pin, and

the control circuit being coupled to the input of the second output buffer via a second bus, wherein the second data bus comprises at least one signal line, the second bus comprising the second temporary memory, and each signal line of the at least one signal line of the second bus comprising a memory element as the second temporary memory.

21. The circuit as claimed in claim 19, wherein the memory circuit comprises a plurality of output buffers which are each coupled to the memory core via an input, and which are each further coupled to the data interface via an output, and which are each further coupled to the command/address interface via their inputs, the memory circuit being adapted to cause the data which is received at the command/address interface to be stored within each of the output buffers of the plurality of output buffers.

22. The circuit as claimed in claim 19, wherein the memory circuit is a GDDRx memory circuit, x designating a GDDR standard.

23. The circuit as claimed in claim 19, wherein the memory circuit is a DRAM memory circuit.

24. A controller comprising:

a command/address interface;

a data interface; and

a synchronization circuit coupled to the command/address interface and to the data interface, and adapted to output a transmit data pattern on the command/address interface, further adapted to receive a receive data pattern from the data interface, and further adapted to synchronize the data interface to a clock on the basis of the transmit data pattern and the receive data pattern.

25. The controller as claimed in claim 24, wherein the synchronization circuit comprises a phase detector adapted to determine a phase position of the receive data pattern.

26. The controller as claimed in claim 25, further comprising a delay circuit coupled to the data interface and adapted to cause the synchronization of the data interface on the basis of the phase position of the receive data pattern.

27. The controller as claimed in claim 26, wherein the data interface comprises a plurality of data lines, each data line of the plurality of data lines comprising a delay circuit adapted to cause the synchronization of the data lines of the data interface on the basis of the phase position of the receive data pattern.

28. The controller as claimed in claim 24, wherein the synchronization circuit is adapted to generate, as the transmit data pattern, a de Bruin data pattern, a clock signal-like data pattern, a random data pattern, or any other pre-determined data pattern.

29. The controller as claimed in claim 24, wherein the memory controller is a GPU.

30. The controller as claimed in claim 24, wherein the memory controller is a DRAM memory controller.

31. A memory system comprising:

a memory circuit comprising

an output buffer comprising an input and an output;

a data interface which is at least in a position to transmit data, the data interface being coupled to the output of the output buffer;

a command/address interface coupled to the input of the output buffer;

a memory core coupled to the input of the output buffer; and

a controller circuit adapted to cause data stored within the output buffer to be output to the data interface upon reception of a first signal, further adapted to cause data stored within the memory core to be output to the input of the output buffer upon reception of a second signal, so that the data is stored within the output buffer, and further adapted to cause provision of data received at the command/address interface to the input of the output buffer upon reception of a third signal, so that the data is stored within the output buffer; and

a memory controller comprising

a command/address interface;

a data interface; and

a synchronization circuit coupled to the command/address interface and to the data interface, and adapted to output a transmit data pattern on the command/address interface, further adapted to receive a receive data pattern from the data interface, and further adapted to synchronize the data interface to a clock on the basis of the transmit data pattern and the receive data pattern,

the data interface of the memory circuit, and the data interface of the memory controller being coupled to one another, and

the command/address interface of the memory circuit being coupled to the command/address interface of the memory controller.

32. A graphics system comprising:

a GDDRx memory circuit, x being a number and designating a GDDR standard, the memory circuit comprising

an output buffer comprising an input and an output;

a data interface which is at least in a position to transmit data, the data interface being coupled to the output of the output buffer;

a command/address interface coupled to the input of the output buffer;

a memory core coupled to the input of the output buffer;

a controller circuit adapted to cause data stored within the output buffer to be output to the data interface upon reception of a signal, further adapted to cause data stored within the memory core to be output to the input of the output buffer upon reception of a second signal, so that the data is stored within the output buffer, and further adapted to cause provision of data received at the command/address interface to the input of the output buffer upon reception of a third signal, so that the data is stored within the output buffer; and

a GPU comprising

a command/address interface;

a data interface; and

a synchronization circuit coupled to the command/address interface and to the data interface, and adapted to output a transmit data pattern on the command/address interface, further adapted to receive a receive data pattern from the data interface, and further adapted to synchronize the data interface to a clock on the basis of the transmit data pattern and the receive data pattern,

the data interface of the GDDRx memory circuit, and the data interface of the GPU being coupled to one;

another, and

the command/address interface of the GDDRx memory circuit being coupled to the command/address interface of the GPU.

33. A method of initializing a circuit, the circuit comprising;

an output buffer comprising an input and an output;

a data interface which is at least in a position to transmit data, the data interface being coupled to the output of the output buffer;

a command/address interface coupled to the input of the output buffer;

a memory core coupled to the input of the output buffer; and

a controller circuit adapted to cause data stored within the output buffer to be output to the data interface upon reception of a first signal, further adapted to cause data stored within the memory core to be output to the input of the output buffer upon reception of a second signal, so that the data is stored within the output buffer, and further adapted to cause provision of data received at the command/address interface to the input of the output buffer upon reception of a third signal, so that the data is stored within the output buffer;

the method comprising;

transmitting a transmit data pattern as data to the command/address interface; and

providing the third signal.

34. A method of initializing a circuit comprising a transmit data pattern, the memory circuit an output buffer comprising an input and an output, a data interface configured to allow at least a transmission of data, a command/address interface, and a memory core, the method comprising:

receiving the transmit data pattern at the command/address interface;

forwarding the transmit data pattern to the output buffer; and

storing the transmit data pattern into the output buffer.

35. The method of initializing a circuit as claimed in claim 34, wherein receiving the transmit data pattern comprises receiving a first part of the transmit data pattern and receiving a second part of the transmit data pattern, and the forwarding of the transmit data pattern comprises temporarily storing the first part of the transmit data pattern and forwarding the temporarily stored first part of the transmit data pattern and the second part of the transmit data pattern.

36. A method of synchronizing a memory system comprising a memory controller and a memory circuit, the method comprising:

generating a transmit data pattern;

outputting the transmit data pattern via a command/address interface of the memory controller;

receiving the transmit data pattern at a command/address interface of the memory circuit;

forwarding the transmit data pattern to an output buffer of the memory circuit;

outputting the transmit data pattern from the output buffer of the memory circuit to a data interface of the memory circuit;

transmitting the transmit data pattern as a receive data pattern to a data interface of the memory controller;

receiving the receive data pattern at the data interface of the memory controller; and

synchronizing the data interface to a clock on the basis of the transmit data pattern and the receive data pattern.

37. The method of synchronizing a memory system as claimed in claim 36, wherein transmitting the transmit data pattern comprises transmitting a first part of the transmit data pattern and transmitting a second part of a transmit data pattern, transmitting the transmit data pattern from the memory controller to the memory circuit comprising transmitting the first part of the transmit data pattern and transmitting the second part of the transmit data pattern, receiving the transmit data pattern at the command/address interface of the memory system comprising receiving the first part of the transmit data pattern and receiving the second part of the transmit data pattern, and forwarding the transmit data pattern comprising temporarily storing the first part of the transmit data pattern and forwarding the temporarily stored first part of the transmit data pattern along with the second part of the transmit data pattern to the output buffer of the memory circuit.

38. A device for synchronizing a memory system comprising a memory controller and a memory circuit, the device comprising:

a generator for generating a transmit data pattern in the memory controller;

a first transmitter for transmitting the transmit data pattern to a command/address interface of the memory controller;

a second transmitter for transmitting the transmit data pattern from the command/address interface of the memory controller to a command/address interface of the memory circuit;

a first receiver for receiving the transmit data pattern from the command/address interface of the memory circuit;

a forwarder for forwarding the transmit data pattern;

a buffer for buffering the forwarded transmit data pattern;

an outputter for outputting the buffered transmit data pattern to a data interface of the memory circuit;

a third transmitter for transmitting the output transmit data pattern to a data interface of the memory controller;

a second receiver for receiving the transmit data pattern as the receive data pattern from the data interface of the memory controller; and

a synchronizer for synchronizing the data interface of the memory controller to a clock on the basis of the transmit data pattern and the receive data pattern.

39. A program comprising a program code, when the program runs on a processor, for performing a method of initializing a circuit, the circuit comprising:

an output buffer comprising an input and an output;

a data interface which is at least in a position to transmit data, the data interface being coupled to the output of the output buffer;

a command/address interface coupled to the input of the output buffer;

a memory core coupled to the input of the output buffer; and

a controller circuit adapted to cause data stored within the output buffer to be output to the data interface upon reception of a first signal, further adapted to cause data stored within the memory core to be output to the input of the output buffer upon reception of a second signal, so that the data is stored within the output buffer, and further adapted to cause provision of data received at the command/address interface to the input of the output buffer upon reception of a third signal, so that the data is stored within the output buffer;

the program comprising;

transmitting a transmit data pattern as data to the command/address interface; and

providing the third signal.

40. A program comprising a program code, when the program runs on a processor, for performing a method of initializing a circuit comprising a transmit data pattern, the circuit comprising an output buffer comprising an input and an output, a data interface adapted to allow at least transmission of data, a command/address interface, and a memory core,

the program comprising:

receiving the transmit data pattern at the command/address interface;

forwarding the transmit data pattern to the output buffer; and

storing the transmit data pattern in the output buffer.

41. A program comprising a program code, when the program runs on a processor, for performing a method of synchronizing a memory system comprising a memory controller and a memory circuit, the program comprising:

generating a transmit data pattern;

outputting the transmit data pattern via a command/address interface of the memory controller;

receiving the transmit data pattern at a command/address interface of the memory circuit;

forwarding the transmit data pattern to an output buffer of the memory circuit;

outputting the transmit data pattern from the output buffer of the memory circuit to a data interface of the memory circuit;

transmitting the transmit data pattern as a receive data pattern to a data interface of the memory controller;

receiving the receive data pattern at the data interface of the memory controller; and

synchronizing the data interface to a clock on the basis of the transmit data pattern and the receive data pattern.