Single-Chip Multi-Media Card/Secure Digital (MMC/SD) Controller Reading Power-On Boot Code from Integrated Flash Memory for User Storage

• US 20080228984A1
• Filed: 05/29/2008
• Published: 09/18/2008
• Est. Priority Date: 12/02/2003
• Status: Active Grant

• Current Assignee: Super Talent Technology, Corporation
• Original Assignee: Super Talent Electronics, Inc.
• Inventors: Ma, Abraham C., Lee, Charles C., Yu, I-Kang
• Granted Patent: US 7,552,251 B2
• Time in Patent Office: Days
• US Class Current: 710/308
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence

Abstract

A Multi-Media Card/Secure Digital (MMC/SD) single-chip flash device contains a MMC/SD flash microcontroller and flash mass storage blocks containing flash memory arrays that are block-addressable rather than randomly-addressable. MMC/SD transactions from a host MMC/SD bus are read by a bus transceiver on the MMC/SD flash microcontroller. Various routines that execute on a CPU in the MMC/SD flash microcontroller are activated in response to commands in the MMC/SD transactions. A flash-memory controller in the MMC/SD flash microcontroller transfers data from the bus transceiver to the flash mass storage blocks for storage. Rather than boot from an internal ROM coupled to the CPU, a boot loader is transferred by DMA from the first page of the flash mass storage block to an internal RAM. The flash memory is automatically read from the first page at power-on. The CPU then executes the boot loader from the internal RAM to load the control program.

Claims

1. A single-chip flash memory drive comprising:

a high speed host interface that connects to a host computer system over a host bus, wherein the host bus is selected from the group consisting of;

a Multi-Media Card (MMC) bus having parallel data lines and a clock, a Secure Digital (SD) bus having parallel data lines and a clock, a Memory-Stick bus;

a Universal Serial Bus (USB), a Peripheral Component Interconnect (PCI) Express bus, an integrated device electronics (IDE) bus, and a Serial ATA (SATA) bus;

a high-speed internal bus with a plurality of components coupled thereupon, the components comprising;

an advanced input/output interface logic configured to facilitate data, control signals and communication to and from the host computer system via the host bus;

a central processing unit (CPU) configured to manage data transfer operations between the host computer system and the single-chip flash memory drive;

at least one flash memory device, configured to conduct data exchanges with a data buffer, wherein each data change is managed by the CPU through block accessible addressing.

2. A flash drive comprising:

a bridge that connects to a host over a high speed host interface bus, and connects to downstream devices over a plurality of interface buses;

wherein the high speed host interface is a Universal Serial Bus (USB), a Peripheral Component Interconnect (PCI) Express bus, an integrated device electronics (IDE) bus, or a Serial ATA (SATA) bus;

wherein the downstream interface buses comprise parallel data buses and clock,

a plurality of single-chip flash memory devices, coupled to the bridge as downstream devices, each single-chip flash device comprising;

a flash microcontroller having a processor;

a main memory coupled to the processor for storing instructions for execution by the processor;

a parallel interface through one of the plurality of interface buses;

a flash-memory controller;

at least one flash memory device, configured to conduct data exchanges, wherein each data exchange is managed by the flash-memory controller;

a direct-memory access (DMA) engine for directly transferring data and instructions over an internal bus among the interface buses, the main memory, the CPU, and the flash-memory controller;

a flash programming engine for initially programming the DMA engine to read an initial program from a first page of a plurality of flash mass storage blocks and write the initial program to the main memory for execution by the processor.

3. A flash drive comprising:

a bridge that connects to a host over a high speed host interface bus, and connects to downstream devices over a plurality of interface buses;

wherein the high speed host interface is an Universal Serial Bus (USB), a Peripheral Component Interconnect (PCI) Express bus, an integrated device electronics (IDE) bus, or a Serial ATA (SATA) bus;

wherein the interface buses comprise a Multi-Media Card (MMC) bus having serial data lines and a clock, or a Secure Digital (SD) bus having serial data lines and a clock;

a plurality of serial single-chip flash memory devices, coupled to the bridge as downstream devices, each serial single-chip flash device comprising;

a serial-flash microcontroller having a processor;

a main memory coupled to the processor for storing instructions for execution by the processor;

a serial interface through one of a plurality of serial buses;

a flash-memory controller;

at least one flash memory device, configured to conduct data exchanges, wherein each data exchange is managed by the flash-memory controller through block-based addressing;

a direct-memory access (DMA) engine for directly transferring data and instructions over an internal bus among the serial interface, the main memory, the processor, and the flash-memory controller; and

a flash programming engine for initially programming the DMA engine to read an initial program from a first page of a plurality of flash mass storage blocks and write the initial program to the main memory for execution by the processor.

4. The flash drive of claim 3 wherein the downstream interface buses comprise a Multi-Media Card (MMC) bus or a Secure Digital (SD) bus.