METHOD OF WIRE BONDING OVER ACTIVE AREA OF A SEMICONDUCTOR CIRCUIT

• US 20080233733A1
• Filed: 10/29/2007
• Published: 09/25/2008
• Est. Priority Date: 12/21/1998
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Lin, Mou-Shiung
• Granted Patent: US 8,138,079 B2
• Time in Patent Office: Days
• US Class Current: 438/617
• CPC Class Codes: H01L 2224/02166 Collar structures
• CPC Class Codes: H01L 2224/023 Redistribution layers [RDL] for bonding areas
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05073 Single internal layer
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05171 Chromium [Cr] as principal constituent
• CPC Class Codes: H01L 2224/05187 Ceramics, e.g. crystalline carbides, nitrides or oxides glass ceramics H01L2224/05188
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05556 in side view
• CPC Class Codes: H01L 2224/05558 conformal layer on a patterned surface
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/4807 of bonding interfaces, e.g. interlocking features
• CPC Class Codes: H01L 2224/48453 of the interface with the bonding area
• CPC Class Codes: H01L 2224/48463 the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
• CPC Class Codes: H01L 2224/48599 Principal constituent of the connecting portion of the wire connector being Gold (Au)
• CPC Class Codes: H01L 2224/48624 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/48644 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48647 : Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/854 : with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
• CPC Class Codes: H01L 2224/85424 : Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/85444 : Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/85447 : Copper (Cu) as principal constituent
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01007 : Nitrogen [N]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/05042 : Si3N4
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor

Abstract

A method and structure are provided to enable wire bond connections over active and/or passive devices and/or low-k dielectrics, formed on an Integrated Circuit die. A semiconductor substrate having active and/or passive devices is provided, with interconnect metallization formed over the active and/or passive devices. A passivation layer formed over the interconnect metallization is provided, wherein openings are formed in the passivation layer to an upper metal layer of the interconnect metallization. Compliant metal bond pads are formed over the passivation layer, wherein the compliant metal bond pads are connected through the openings to the upper metal layer, and wherein the compliant metal bond pads are formed substantially over the active and/or passive devices. The compliant metal bond pads may be formed of a composite metal structure.

Claims

1. A method for fabricating an integrated circuit die with a wirebonded wire, comprising:

providing a semiconductor substrate, an active device in or over said semiconductor substrate, a first interconnect metal layer over said semiconductor substrate, an intermetal dielectric layer over said first interconnect metal layer, a second interconnect metal layer over said intermetal dielectric layer, and a passivation layer over said second interconnect metal layer, wherein a first opening in said passivation layer exposes a first pad of said second interconnect metal layer;

forming a second pad over said semiconductor substrate, wherein said second pad is connected to said first pad through said first opening in said passivation layer, and wherein said forming said second pad comprises forming a glue/barrier layer over said first pad and over said passivation layer, forming a seed layer on said glue/barrier layer, forming a photoresist layer on said seed layer, wherein a second opening in said photoresist layer exposes said seed layer, electroplating a copper layer on said seed layer exposed by said second opening in said photoresist layer, wherein said copper layer has a thickness greater than 1 micrometer, electroplating a nickel layer on said copper layer in said second opening, wherein said nickel layer has a thickness greater than 0.5 micrometer, electroless plating a gold layer on said nickel layer in said second opening, wherein said gold layer has a thickness greater than 0.1 micrometer, after said electroless plating said gold layer, removing said photoresist layer, etching said seed layer not under said gold layer, and etching said glue/barrier layer not under said gold layer; and

wirebonding said wirebonded wire to said second pad, wherein a contact area between said second pad and said wirebonded wire is directly over said active device.

2. The method of claim 1, after said providing said semiconductor substrate, further comprising forming a polymer layer on said passivation layer, followed by said forming said second pad on said polymer layer.

3. The method of claim 1, wherein said forming said glue/barrier layer comprises sputtering a titanium-containing layer over said first pad and over said passivation layer.

4. The method of claim 1, wherein said forming said glue/barrier layer comprises sputtering a chromium-containing layer over said first pad and over said passivation layer.

5. The method of claim 1, wherein said first opening has a width between 40 μ

m and 100 μ

m.

6. The method of claim 1, wherein said forming said glue/barrier layer comprises a sputtering process.

7. The method of claim 1, wherein said forming said seed layer comprises a sputtering process.

8. The method of claim 1, wherein said passivation layer comprises a nitride layer and an oxide layer.

9. The method of claim 1, wherein said seed layer comprises copper.

10. A method for fabricating an integrated circuit die with a wirebonded wire, comprising:

providing a semiconductor substrate, an active device in or over said semiconductor substrate, a first interconnect metal layer over said semiconductor substrate, an intermetal dielectric layer over said first interconnect metal layer, a second interconnect metal layer over said intermetal dielectric layer, and a passivation layer over said second interconnect metal layer, wherein a first opening in said passivation layer exposes a first pad of said second interconnect metal layer;

forming a polymer layer on said passivation layer, wherein said forming said polymer layer comprises depositing a photosensitive polymer on said passivation layer;

forming a second opening in said polymer layer, wherein said second opening exposes said first pad;

forming a second pad over said polymer layer, wherein said second pad is connected to said first pad through said second opening and said first opening, and wherein said forming said second pad comprises forming a glue/barrier layer over said first pad and over said polymer layer, forming a seed layer on said glue/barrier layer, forming a photoresist layer on said seed layer, wherein a third opening in said photoresist layer exposes said seed layer, electroplating a copper layer on said seed layer exposed by said third opening, wherein said copper layer has a thickness greater than 1 micrometer, electroplating a nickel layer on said copper layer in said third opening, wherein said nickel layer has a thickness greater than 0.5 micrometer, electroless a gold layer on said nickel layer in said third opening, wherein said gold layer has a thickness greater than 0.1 micrometer, after said electroless plating said gold layer, removing said photoresist layer, etching said seed layer not under said gold layer, and etching said glue/barrier layer not under said gold layer; and

wirebonding said wirebonded wire to said second pad, wherein a contact area between said second pad and said wirebonded wire is directly over said active device.

11. The method of claim 10, wherein said passivation layer comprises a nitride layer and an oxide layer.

12. The method of claim 10, wherein said forming said polymer layer comprises forming a polyimide layer on said passivation layer.

13. The method of claim 10, wherein said forming said polymer layer comprises forming a benzocyclobutene (BCB) layer on said passivation layer.

14. The method of claim 10, wherein said forming said glue/barrier layer comprises a sputtering process.

15. The method of claim 10, wherein said forming said seed layer comprises a sputtering process.

16. The method of claim 10, wherein said forming said polymer layer comprises a spin-coating process.

17. The method of claim 10, wherein said forming said glue/barrier layer comprises sputtering a titanium-containing layer over said first pad and over said polymer layer.

18. The method of claim 10, wherein said forming said glue/barrier layer comprises sputtering a chromium-containing layer over said first pad and over said polymer layer.

19. The method of claim 10, wherein said seed layer comprises copper.

20. A method for fabricating an integrated circuit die with a wirebonded wire, comprising:

providing a semiconductor substrate, an active device in or over said semiconductor substrate, a first interconnect metal layer over said semiconductor substrate, an intermetal dielectric layer over said first interconnect metal layer, a second interconnect metal layer over said intermetal dielectric layer, and a passivation layer over said second interconnect metal layer, wherein a first opening in said passivation layer exposes a first pad of said second interconnect metal layer, and wherein said passivation layer comprises an oxide layer and a nitride layer wherein said nitride layer is over said oxide layer;

forming a polymer layer on said passivation layer, wherein said forming said polymer layer comprises depositing a photosensitive polymer on said passivation layer;

forming a second opening in said polymer layer, wherein said second opening exposes said first pad;

forming a second pad over said polymer layer, wherein said second pad is connected to said first pad through said second opening and said first opening, and wherein said forming said second pad comprises forming a glue/barrier layer over said first pad and over said polymer layer, forming a first copper layer on said glue/barrier layer, electroplating a second copper layer on said first copper layer, wherein said second copper layer has a thickness greater than 1 micrometer, electroplating a nickel layer on said second copper layer, wherein said nickel layer has a thickness greater than 0.5 micrometer, forming a gold layer on said nickel layer, wherein said gold layer has a thickness greater than 0.1 micrometer, etching said first copper layer not under said gold layer, and etching said glue/barrier layer not under said gold layer; and

wirebonding said wirebonded wire to said second pad, wherein a contact area between said second pad and said wirebonded wire is directly over said active device, wherein the position of said contact area from a top view is different from that of said first pad.

21. The method of claim 20, wherein said forming said polymer layer comprises forming a polyimide layer on said passivation layer.

22. The method of claim 20, wherein said forming said polymer layer comprises forming a benzocyclobutene (BCB) layer on said passivation layer.

23. The method of claim 20, wherein said forming said polymer layer comprises a spin-coating process.

24. The method of claim 20, wherein said forming said glue/barrier layer comprises a sputtering process.

25. The method of claim 20, wherein said forming said first copper layer comprises a sputtering process.