Vertical system integration

• US 20080237591A1
• Filed: 05/09/2008
• Published: 10/02/2008
• Est. Priority Date: 08/08/2002
• Status: Active Grant

• Current Assignee: ELM TECHNOLOGY CORPORATION
• Original Assignee: ELM TECHNOLOGY CORPORATION
• Inventors: Leedy, Glenn J.
• Granted Patent: US 8,587,102 B2
• Time in Patent Office: Days
• US Class Current: 257/48
• CPC Class Codes: B81B 7/02 containing distinct electrical or optical devices of particular relevance for their function, e.g. microelectro-mechanical systems [MEMS] B81B7/04 takes precedence
• CPC Class Codes: B81C 1/00238 Joining a substrate with an electronic processing unit and a substrate with a micromechanical structure
• CPC Class Codes: B81C 1/00246 Monolithic integration, i.e. micromechanical structure and electronic processing unit are integrated on the same substrate
• CPC Class Codes: B81C 2203/0771 Stacking the electronic processing unit and the micromechanical structure
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: H01L 21/8252 the substrate being a semiconductor, using III-V technology H01L21/8258 takes precedence
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 2223/54453 for use prior to dicing
• CPC Class Codes: H01L 2223/6677 for antenna, e.g. antenna included within housing of semiconductor device antennas per se H01Q
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06589 Thermal management, e.g. cooling
• CPC Class Codes: H01L 2225/06596 Structural arrangements for testing testing or measuring during manufacture or treatment H01L22/00; testing electrical properties or locating electrical faults G01R31/00
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/52 Arrangements for conducting electric current within the device in operation from one component to another , i.e. interconnections, e.g. wires, lead frames optical interconnections G02B6/00
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 27/0688 : Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/105 : including field-effect components
• CPC Class Codes: H01L 27/118 : Masterslice integrated circuits
• CPC Class Codes: H01L 27/11803 : using field effect technology
• CPC Class Codes: H01L 27/1203 : the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1463 : Pixel isolation structures
• CPC Class Codes: H01L 27/14643 : Photodiode arrays; MOS imagers
• CPC Class Codes: H01L 27/14683 : Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof not peculiar thereto H01L21/00
• CPC Class Codes: H01L 29/40114 : the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/40117 : the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/42324 : Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/42328 : with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/66825 : with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/66833 : with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7827 : Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7831 : with multiple gate structure FinFETs or MuGFETs H01L29/7855, thin film transistors H01L29/78645
• CPC Class Codes: H01L 29/78648 : arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/7881 : Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H04W 4/80 : Services using short range communication, e.g. near-field communication [NFC], radio-frequency identification [RFID] or low energy communication
• CPC Class Codes: H10B 12/00 : Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/20 : DRAM devices comprising floating-body transistors, e.g. floating-body cells
• CPC Class Codes: H10B 12/30 : DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
• CPC Class Codes: H10B 69/00 : Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
• CPC Class Codes: H10B 99/00 : Subject matter not provided for in other groups of this subclass

Abstract

The Vertical System Integration (VSI) invention herein is a method for integration of disparate electronic, optical and MEMS technologies into a single integrated circuit die or component and wherein the individual device layers used in the VSI fabrication processes are preferably previously fabricated components intended for generic multiple application use and not necessarily limited in its use to a specific application. The VSI method of integration lowers the cost difference between lower volume custom electronic products and high volume generic use electronic products by eliminating or reducing circuit design, layout, tooling and fabrication costs.

Claims

1. A stacked integrated circuit comprising:

a first integrated circuit layer; and

a second integrated circuit layer overlying the first integrated circuit layer;

wherein at least one of the first and second integrated circuit layers is fabricated according to a completed physical IC design or fabricated IC selected from a design library of completed physical IC designs or fabricated ICs.

2. The apparatus of claim 1, wherein the first and second circuit layers includes at least one of the following:

a microprocessor, PLD or FPGA circuitry, a passive device array, a DSP, a SERDES, I/O circuitry, memory, and a graphics processor.

3. The apparatus of claim 1, having at least partial logic circuit redundancy between different layers.

4. The apparatus of claim 1, comprising at least three layers, each of the three layers being either a memory layer or a PLD or FPGA circuit layer.

5. The apparatus of claim 4, comprising a plurality of memory layers and a plurality of PLD or FPGA circuit layers.

6. The apparatus of claim 1, wherein the stacked integrated circuit is provided with wireless interconnection capability.

7. The apparatus of claim 1, comprising a plurality of circuit layers bonded together such that no circuitry of a circuit layer of the stacked integrated circuit is external to the stacked integrated circuit.

8. The apparatus of claim 1, wherein at least one of the circuit device layers comprises electronic circuitry.

9. The apparatus of claim 1, wherein at least one of the circuit device, layers comprises optical circuitry.

10. The apparatus of claim 1, wherein at least one of the circuit device layers comprises a MEMS device.

11. The apparatus of claim 1, comprising IC devices fabricated on the backside of one or more circuit layers.

12. The apparatus of claim 11, wherein the IC devices comprise at least one of the following:

transistors, memory cells, resistors, capacitors, inductors, radio frequency antennas and horizontal interconnections.

13. The apparatus of claim 11, wherein the IC devices comprise at least two of the following:

transistors, memory cells, resistors, capacitors, inductors, radio frequency antennas and horizontal interconnections.

14. The apparatus of claim 11, wherein the IC devices comprise all of the following:

transistors, memory cells, resistors, capacitors, inductors, radio frequency antennas and horizontal interconnections.

15. The apparatus of claim 1, comprising a plurality of circuit layers including at least two of the following:

electronic, optical and MEMS circuit layers.

16. The apparatus of claim 1, comprising IC devices fabricated on the backside of one or more circuit layers.

17. The apparatus of claim 1, wherein a dielectric layer is deposited on the backside of one or more the circuit layers to enhance electrical isolation of an underlying semiconductor device layer.

18. The apparatus of claim 1, wherein IC device fabrication is performed on the backside of one or more circuit layers to complete the fabrication of IC devices partially formed on the front side of the one or more circuit layers.

19. The apparatus of claim 1, wherein IC fabrication is performed on the backside of one or more the circuit layers to fabricate one or more layer memory layers.

20. The apparatus of claim 19, wherein the memory layers consist of at least one of MRAM, PRAM, ferroelectric or dendritic memory.

21. The apparatus of claim 1, wherein the circuit layers are bonded using bonding layers made from two or more metal films one of which has a lower melting point and which will diffuse with an immediately adjacent film.

22. The apparatus of claim 21, wherein bonding layers form a diffused metal film having a higher melting point than the lower melting point metal film.

23. The apparatus of claim 1, wherein the circuit layers are bonded using bonding layers made from two or more metal films one of which has a lower melting temperature and which will diffuse with an immediately adjacent film.

24. The apparatus of claim 1, wherein at least one of the circuit layers is a programmable tester for testing of the stacked IC during burn-in or during its useful life.

25. The apparatus of claim 1, wherein all surfaces of the circuit layers with circuitry thereon are internal to the stacked IC whereby the stacked IC is its own packaging.

26. The apparatus of claim 25, wherein the bonding layers of one or more of the circuit layers form hermetic seals.

27. The apparatus of claim 1, comprising a plurality of circuit layers wherein two or more circuit layers have similar functioning circuitry in a vertical overlapping position.

28. The apparatus of claim 1, wherein the circuitry on the circuit layers is reconfigurable by the use of vertical interconnections between the circuit layers.

29. The apparatus of claim 1, comprising one or more vertical interconnections between the circuit layers having cross-sectional areas that are at least two times larger than any horizontal signal interconnection.

30. The apparatus of claim 1, wherein some of the circuit layers are not designed specifically for the particular stacked IC.

31. The apparatus of claim 1, wherein art application-specific function of the stacked IC is derived from the choice and quantity of circuit layers front previously-fabricated, non-application-specific circuit layers.

32. The apparatus of claim 1, wherein one or more of the circuit layers have portions of horizontal interconnections that are free-standing.

33. The apparatus of claim 1, wherein one or more of the circuit layers have portions of horizontal interconnections that are without the mechanical support of a dielectric.

34. The apparatus of claim 1, wherein interconnections of circuitry on at least one of the circuit layers are chanced by interconnections on the backside of the circuit layer.

35. The apparatus of claim 1, wherein one or more transistor gates of at least one circuit layer is back biased by forming a contact on the backside of the at least one circuit layer opposite the one or more transistor gates.

36. The apparatus of claim 1, wherein I/O drivers, for the stacked IC are physically on a separate circuit layer or on the backside of one of the circuit layers.

37. The apparatus of claim 1, wherein in one of the circuit layers dielectric has been predominately removed leaving free-standing metal horizontal and vertical interconnections.

38. The apparatus of claim 1, wherein one of the circuit layers contains a predominately free-standing Rf antenna.

39. The apparatus of claim 1, wherein one of the circuit layers comprises a MEMS device.

40. The apparatus of claim 39, wherein the first circuit layer is a MEMS device.

41. The apparatus of claim 39, wherein the MEMS device is fabricated as part of a circuit layer after bonding of the circuit layer to another circuit layer.

42. The apparatus of claim 1, wherein one optical circuit layer couples signals into an electronic circuit layer.

43. The apparatus of claim 1, wherein one of the circuit layers is a generically programmable automatic testing circuit layer for testing one or more of the circuit layers of the stacked IC.

44. The apparatus of claim 1, comprising a plurality of circuit layers with redundant circuits wherein an interconnection wire length between redundant circuits is approximately equal to or less than a thickness of the stacked IC.

45. The apparatus of claim 1, comprising a plurality of circuit layers including wireless circuitry for creating multiple data transmission paths between a plurality of stacked ICs, and means for changing one or more wireless data transmission paths between any two stacked ICs as needed.

46. The apparatus of claim 1, comprising a plurality of circuit layers including a plurality of wireless circuits wherein the wireless circuits are used to create a plurality of data transmission paths.

47. The apparatus of claim 1, comprising circuitry for performing full-wafer test and burn-in.

48. The apparatus of claim 1, comprising memory control logic and memory circuit layers wherein at least one circuit layer has memory control logic circuitry enabling reconfiguration of the memory circuit layers of the stacked IC.

49. The apparatus of claim 1, comprising memory control logic and memory circuit layers wherein at least one circuit layer has memory control logic circuitry enabling the use of a variable amount of the memory of the stacked IC.

50. The apparatus of claim 1, comprising a credit-card-shaped enclosure enclosing the stacked IC.

51. The apparatus of claim 1, comprising a sensing device with sensor devices separated and overlying processing electronics of the sensor devices.

52. The apparatus of claim 1, comprising a stacked programmable logic device having a plurality of circuit layers wherein there is at least one each of a programmable gate circuit layer, a routing circuit layer and a memory circuit layer.

53. The apparatus of claim 1, comprising a stacked programmable logic device having a plurality of circuit layers wherein there is at least one circuit layer comprising automatic test electronics.

54. The apparatus of claim 1, comprising a plurality of circuit layers with processors thereon wherein a non-blocking cross bar interconnects the processors and is integrated onto the circuit layers of the stacked IC.

55. The apparatus of claim 1, comprising a plurality of circuit layers wherein one or more of the circuit layers comprises analog circuitry elements and one or more of the circuit layers comprises reconfigurable circuitry which can be programmed to interconnect the analog circuitry elements to circuitry on one or more of the circuit layers of the stacked IC.

56. The apparatus of claim 1, comprising a plurality of circuit layers wherein one or more of the circuit layers comprises passive circuitry elements and one or more of the circuit layers comprises reconfigurable circuitry-which can be programmed to interconnect the passive circuitry elements to circuitry on one or more of the circuit layers of the stacked IC.