Integrated Memory Management Device and Memory Device

• US 20080244165A1
• Filed: 03/27/2008
• Published: 10/02/2008
• Est. Priority Date: 03/28/2007
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Kunimatsu, Atsushi
• Granted Patent: US 8,261,041 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/10 Address translation
• CPC Class Codes: G06F 12/1045 associated with a data cache

Abstract

An example of a device comprises a first MMU converting a logical address into a physical address for a cache, a controller accessing the cache based on the physical address for the cache, a first storage storing history data showing an access state to a main memory outside a processor, a second storage storing relation data showing a relationship between a logical address and a physical address in the main memory, and a second MMU converting a logical address into a physical address for the main memory based on the history and relation data and accessing the main memory based on the physical address for the main memory. The first and second MMU, controller, first storage, second storage are included in the processor.

Claims

1. An integrated memory management device comprising:

a first memory management unit converting a logical address for accessing a cache memory into a physical address for accessing the cache memory, and included in a processor;

a cache controller accessing the cache memory based on the physical address for accessing the cache memory, and included in the processor;

an access history storage storing access history data showing an access state to a main memory outside the processor, and included in the processor;

an address relation storage storing address relation data showing a relationship between a logical address and a physical address in the main memory, and included in the processor; and

a second memory management unit converting a logical address for accessing the main memory into a physical address for accessing the main memory based on the access history data and the address relation data, and accessing the main memory based on the physical address for accessing the main memory, and further, included in the processor.

2. The device according to claim 1, wherein the main memory is a NAND Flash™

main memory.

3. The device according to claim 1, wherein the access history data includes at least one of a rewrite frequency for each location in the main memory, a defective location in the main memory and a location stored with data in the main memory,

the second memory management unit selects a storage location in the main memory based on the access history data stored in the access history storage.

4. The device according to claim 3, wherein the access history data includes a rewrite frequency for each location in the main memory,

the second memory management unit selects a location having a rewrite frequency less than a predetermined frequency in the main memory based on the access history data, and stores data in the selected location.

5. The device according to claim 1, wherein the second memory management unit reads part or all of main memory data including at least one of a rewrite frequency for each location in the main memory, a defective location in the main memory and a location stored with data in the main memory, which are stored in the main memory, and stores part or all of the main memory history data as the access history data in the access history storage.

6. The device according to claim 5, wherein the second memory management unit updates the access history data of the access history storage when data write to the main memory is generated from the second memory management unit, and updates the main memory history data of the main memory based on the access history data stored in the access history storage.

7. The device according to claim 1, wherein the second memory management unit includes the address relation storage.

8. The device according to claim 1, wherein the second memory management unit stores part or all of an address conversion table stored in the main memory and showing a relationship between a logical address and a physical address as the address relation data in the address relation storage.

9. The device according to claim 8, wherein the second memory management unit updates the address relation data when data write to the main memory is generated from the second memory management unit, and updates the address conversion table of the main memory based on the address relation data.

10. The device according to claim 1, wherein when read target data is not stored in the cache memory, the second memory management unit reads the read target data from the main memory to store the read target data in the cache memory via the cache controller, stores address relation data corresponding to the read target data in the address relation storage, and stores access history data corresponding to the read target data in the access history storage.

11. The device according to claim 1, further comprising:

an integrated memory management unit integrating the first and second memory management units.

12. The device according to claim 1, wherein the cache controller controls access to a plurality of cache memories including the cache memory.

13. The device according to claim 12, wherein at least one of said plurality of the cache memories is provided outside the processor.

14. The device according to claim 1, wherein part of the cache memory is used as the access history storage and the access relation storage.

15. An integrated memory management device comprising:

a first memory management unit converting a logical address for accessing a cache memory into a physical address for accessing the cache memory, and included in a processor;

an access history storage storing access history data showing an access state to a main memory outside the processor, and included in the processor;

an address relation storage storing address relation data showing a relationship between a logical address and a physical address in the main memory, and included in the processor;

a second memory management unit converting a logical address for accessing the main memory into a physical address for accessing the main memory based on the access history data and the address relation data, and included in the processor; and

a cache controller accessing the cache memory based on a physical address for accessing the cache memory, and accessing the main memory based on a physical address for accessing the main memory, and included in the processor.

16. The device according to claim 15, wherein the cache controller updates the access history data of the access history storage when data write to the main memory is generated from the cache controller, and updates the main memory history data of the main memory based on the access history data stored in the access history storage.

17. The device according to claim 15, wherein the cache controller updates the address relation data when data write to the main memory is generated from the cache controller, and updates the address conversion table of the main memory based on the address relation data.

18. The device according to claim 15, wherein when read target data is not stored in the cache memory, the cache controller reads the read target data from the main memory to store the read target data in the cache controller, stores address relation data corresponding to the read target data in the address relation storage, and stores access history data corresponding to the read target data in the access history storage.

19. A memory device comprising:

a plurality of cache memories provided in each of a plurality of processors, and accessed based on a logical address of processes executed by each of the processors;

a main memory provided outside the processors, and including a page table, which executes writing or reading at a unit called a page, and collectively executes erasing at a unit of a plurality of pages called a block, and further, manages an integrated physical address with respect to the processes, and further, provided with a wear leveling counter in a redundancy area; and

a MMU interposed between the processors and the main memory, and making a conversion from a process level logical address to a physical address based on the page table and a conversion from a logical address to a physical address for executing wear leveling of a page or block unit of the main memory based on the wear leveling counter,

the main memory having the same page size as the MMU or a page size of integer multiples of the MMU, and

page transfer between the cache memories and the main memory being collectively made at a block unit of the main memory.

20. The device according to claim 19, wherein the processors and the MMU are connected via a network, and the logical address includes an address on the network, a processor ID and a process ID, and a process internal logical address.