NOISE CHECKING METHOD AND APPARATUS, AND COMPUTER-READABLE RECORDING MEDIUM IN WHICH NOISE CHECKING PROGRAM IS STORED

• US 20080250366A1
• Filed: 06/18/2008
• Published: 10/09/2008
• Est. Priority Date: 12/22/2005
• Status: Active Grant

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: ISHIKAWA, Yoichiro
• Granted Patent: US 7,882,466 B2
• Time in Patent Office: Days
• US Class Current: 716/5
• CPC Class Codes: G01R 31/31709 Jitter measurements; Jitter generators measuring jitter, noise figure or signal-to-noise ratio per se G01R29/26; analysis of tester signals G01R31/31901
• CPC Class Codes: G06F 30/3312 Timing analysis
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: H01L 27/0203 Particular design considerations for integrated circuits

Abstract

There is provided a technique in which internal wires of a large cell are spuriously patterned and treated as object of a noise check. Internal wires of a large cell are spuriously determined based on terminal information and wiring forbidden information of the large cell and are added to chip wires to be checked, from which an object wire to be checked and at least one affecting wire are selected, a noise value representing a degree at which the at least one affecting wire induces noise onto the signal of the object wire is calculated and the noise check is performed on the basis of the calculated noise check.

Claims

1. A noise checking method, in designing an integrated circuit, performed on a result of cell arrangement of a plurality of cells including a standard cell and a large cell on a chip of the integrated circuit or on a result of inter-cell wiring among the plurality of cells arranged on the chip, said method comprising:

extracting terminal information about one or more terminals of the large cell and wiring forbidden information about one or more wiring forbidden areas each formed on or inside of the large cell from a library which provides the terminal information and the wiring forbidden information;

spuriously determining one or more internal wires of the large cell based on the terminal information and the wiring forbidden information extracted in said step of extracting, and adding the internal wires determined into chip wires to be checked;

selecting an object wire to be checked and at least one affecting wire from the chip wires to which the internal wires determined are added in said step of determining;

calculating a noise value representing a degree at which the at least one affecting wire induces noise onto the object wire; and

carrying out a noise check on the object wire based on the noise value calculated in said step of calculating.

7. A noise checking method according to claim 1, wherein if one of the internal wires spuriously determined in said step of determining is connected to one of the terminals of the large cell, the one internal wire is regarded as an extension portion of a chip wire connected to the one terminal.

8. A noise checking method according to claim 1, wherein at least two internal wires, each of which is in one of the large cells which are contiguously arranged, are selected as the object wire and the at least one affecting wire in said step of selecting, and the noise check is performed on the at least two internal wires selected.

9. A noise checking method according to claim 8, wherein information about an error occurring position obtained through the noise check performed on the at least two internal wires in said step of performing the noise check is output in the form of relative coordinates to an origin of each of the large cells.

2. A noise checking method, in designing an integrated circuit, performed on a result of cell arrangement of a plurality of cells including a standard cell and a large cell on a chip of the integrated circuit or on a result of inter-cell wiring among the plurality of cells arranged on the chip, said method comprising:

extracting terminal information about one or more terminals of the large cell, wiring forbidden information about one or more wiring forbidden areas each formed on or inside of the large cell, and at least one of maximum drivability and minimum drivability of each of one or more drivers used in the large cell from a library which provides the terminal information, the wiring forbidden information, and the maximum drivability and the minimum drivability of each of the drivers;

spuriously determining one or more internal wires of the large cell based on the terminal information and the wiring forbidden information extracted in said step of extracting, and adding the internal wires determined into chip wires to be checked;

selecting an object wire to be checked and at least one affecting wire from the chip wires to which the internal wires determined are added in said step of determining;

calculating a noise value representing a degree at which the at least one affecting wire induces noise onto the object wire on the basis of the at least one of the maximum drivability and the minimum drivability extracted in said step of extracting; and

carrying out a noise check on the object wire based on the noise value calculated in said step of calculating.

3. A noise checking method according to claim 2, wherein if a chip wire having the large cell which functions as a driver is selected as the object wire in said step of selecting, the noise value is calculated based on the minimum drivability extracted for the large cell in said step of calculating.

4. A noise checking method according to claim 2, wherein if a chip wire having the large cell which functions as a driver is selected as the at least one affecting wire in said step of selecting, the noise value is calculated based on the maximum drivability extracted for the large cell in said step of calculating.

5. A noise checking method according to claim 2, wherein if one of the internal wires of the large cell which is not directly connected to one of the terminals of the large cell is selected as the object wire in said step of selecting, the noise value is calculated based on the minimum drivability extracted for the large cell in said step of calculating.

6. A noise checking method according to claim 2, wherein if one of the internal wires of the large cell which is not directly connected to one of the terminals of the large cell is selected as the at least one affecting wire in said step of selecting, the noise value is calculated based on the maximum drivability extracted for the large cell in said step of calculating.

10. A noise checking apparatus for performing, in designing an integrated circuit, a noise check on a result of cell arrangement of a plurality of cells including a standard cell and a large cell on a chip of the integrated circuit or on a result of inter-cell wiring among the plurality of cells arranged on the chip, said apparatus comprising:

an extracting section extracting terminal information about one or more terminals of the large cell and wiring forbidden information about one or more wiring forbidden areas each formed on or inside of the large cell from a library which provides the terminal information and the wiring forbidden information;

an internal wiring determining section spuriously determining one or more internal wires of the large cell based on the terminal information and the wiring forbidden information extracted by said extracting section, and adding the internal wires determined into chip wires to be checked; and

a noise checking section selecting an object wire to be checked and at least one affecting wire from the chip wires to which the internal wires determined are added by said internal wiring determining section, calculating a noise value representing a degree at which the at least one affecting wire induces noise onto the object wire, and carrying out the noise check on the object wire based on the noise value calculated.

12. A noise checking apparatus according to claim 10, wherein if one of the internal wires spuriously determined by said internal wiring determining section is connected to one of the terminals of the large cell, the one internal wire is regarded as an extension portion of a chip wire connected to the one terminal.

13. A noise checking apparatus according to claim 10, wherein said noise checking section selects at least two internal wires each of which is in one two of the large cells which are contiguously arranged as the object wire and the at least one affecting wire and performs the noise check on the at least two internal wires.

14. A noise checking apparatus according to claim 13, wherein said noise checking section outputs relative coordinates to an origin of each of the large cells, which relative coordinates represent information about an error occurring position obtained through the noise check performed on the at least two internal wires.

11. A noise checking apparatus for performing, in designing an integrated circuit, a noise check on a result of cell arrangement of a plurality of cells including a standard cell and a large cell on a chip of the integrated circuit or on a result of inter-cell wiring among the plurality of cells arranged on the chip, said apparatus comprising:

an extracting section extracting terminal information about one or more terminals of the large cell, wiring forbidden information about one or more wiring forbidden areas each formed on or inside of the large cell, and at least one of maximum drivability and minimum drivability of each of one or more drivers used in the large cell from a library which provides the terminal information, the wiring forbidden information, and the maximum drivability and the minimum drivability of each of the drivers;

an internal wire determining section spuriously determining one or more internal wires of the large cell based on the terminal information and the wiring forbidden information extracted by said extracting section, and adding the internal wires determined into chip wires to be checked; and

a noise checking section selecting an object wire to be checked and at least one affecting wire from the chip wires to which the internal wires determined are added by said internal wiring determining section, calculating a noise value representing a degree at which the at least one affecting wire induces noise onto the object wire on the basis of the at least one of the maximum drivability and the minimum drivability extracted by said extracting section, and carrying out the noise check on the object wire based on the noise value calculated.

15. A computer-readable recording medium in which a noise checking program to function a computer as a noise checking apparatus to perform, in designing an integrated circuit, a noise checking on a result of cell arrangement of a plurality of cells including a standard cell and a large cell on a chip of the integrated circuit chip or on a result of inter-cell wiring among the plurality of cells arranged on the chip is stored, wherein said program instructs the computer to function as:

an extracting section extracting terminal information about one or more terminals of the large cell and wiring forbidden information about one or more wiring forbidden areas each formed on or inside of the large cell from a library which provides the terminal information and the wiring forbidden information;

an internal wiring determining section spuriously determining one or more internal wires of the large cell based on the terminal information and the wiring forbidden information extracted by said extracting section, and adding the internal wires determined into chip wires to be checked; and

a noise checking section selecting an object wire to be checked and at least one affecting wire from the chip wires to which the internal wires determined are added by said internal wiring determining section, calculating a noise value representing a degree at which the at least one affecting wire induces noise onto the object wire, and carrying out a noise check on the object wire based on the noise value calculated.

17. A computer-readable recording medium according to claim 15, wherein if one of the internal wires spuriously determined by said internal wiring determining section is connected to one of the terminals of the large cell, said program instructs the computer to regard the one internal wire as an extension portion of a chip wire which connected to the terminal.

18. A computer-readable recording medium according to claim 15, wherein when said program instructs the computer to function as said noise checking section, said program instructs the computer to select at least two internal wires, each of which is in one of the large cells which are contiguously arranged, as the object wire and the at least one affecting wire and perform the noise check on the at least two internal wires.

19. A computer-readable recording medium according to claim 18, wherein when said program instructs the computer to function as said noise checking section, said program instructs the computer to output relative coordinates to an origin of each of the large cells, which relative coordinates represent information about an error occurring position obtained through the noise check performed on the at least two internal wires.

16. A computer-readable recording medium in which a noise checking program to function a computer as a noise checking apparatus to perform, in designing an integrated circuit, a noise checking on a result of cell arrangement of a plurality of cells including a standard cell and a large cell on a chip of the integrated circuit or on a result of inter-cell wiring among the plurality of cells arranged on the chip is stored, wherein said program instructs the computer to function as:

an extracting section extracting terminal information about one or more terminals of the large cell, wiring forbidden information about one or more wiring forbidden areas each formed on or inside of the large cell, and at least one of maximum drivability and minimum drivability of each of one or more drivers used in the large cell from a library which provides the terminal information, the wiring forbidden information, and the maximum drivability and the minimum drivability of each of the drivers;

an internal wire determining section spuriously determining one or more internal wires of the large cell based on the terminal information and the wiring forbidden information extracted by said extracting section, and adding the internal wires determined into chip wires to be checked; and

a noise checking section selecting an object wire to be checked and at least one affecting wire from the chip wires to which the internal wires determined are added by said internal wiring determining section, calculating a noise value representing a degree at which the at least one affecting wire induces noise onto the object wire on the basis of the at least one of the maximum drivability and the minimum drivability extracted by said extracting section, and carrying out a noise check on the object wire based on the noise value calculated.