EXECUTING MULTIPLE THREADS IN A PROCESSOR

• US 20080250422A1
• Filed: 04/05/2007
• Published: 10/09/2008
• Est. Priority Date: 04/05/2007
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Lewis, Russell Lee
• Granted Patent: US 7,853,950 B2
• Time in Patent Office: Days
• US Class Current: 718/107
• CPC Class Codes: G06F 9/4881 Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues

Abstract

Provided are a method, system, and program for executing multiple threads in a processor. Credits are set for a plurality of threads executed by the processor. The processor alternates among executing the threads having available credit. The processor decrements the credit for one of the threads in response to executing the thread and initiates an operation to reassign credits to the threads in response to depleting all the thread credits.

Claims

1. An article of manufacture comprising code executed by a processor to access buffers and perform operations, the operations comprising:

setting credits in the buffers for a plurality of threads executed by the processor;

alternating among executing the threads having available credit;

decrementing the credit for one of the threads in response to executing the thread; and

initiating an operation to reassign credits to the threads in response to depleting all the thread credits.

2. The article of manufacture of claim 1, wherein initiating the operation to reassign the credits comprises:

executing a replenish thread in response to depleting all the thread credits, wherein the replenish thread resets the thread credits; and

alternating among executing the threads having available credit in response to the replenish thread resetting the thread credits.

3. The article of manufacture of claim 2, wherein when the threads have available credits, the replenish thread is indicated to not execute until all the thread credits are depleted, and wherein the operations further comprise:

indicating that the replenish thread is to execute in response to executing the replenish thread when all the thread credits are depleted; and

indicating that the replenish thread is not to execute until all the thread credits are depleted in response to resetting the thread credits.

4. The article of manufacture of claim 1, wherein the thread credits are maintained in processor buffers, wherein the operations further comprise:

executing an operating system scheduler to configure the processor to execute the threads and set the thread credits.

5. The article of manufacture of claim 4, wherein the operations further comprise:

executing the operating system scheduler to allocate main memory addresses to the processor for the processor to use as virtual processor buffers to store status and the thread credits for designated threads, wherein the processor buffers for a first set of threads are maintained in the virtual processor buffers and the processor buffers for a second set of threads are maintained in the processor.

6. The article of manufacture of claim 5, wherein the operations further comprise:

determining threads whose status and credits are in the processor buffers to swap to virtual processor buffers and the status and credits of threads in the virtual processor buffer to swap to the processor buffers.

7. The article of manufacture of claim 1, wherein the operations further comprise:

executing a pause instruction when executing one thread; and

indicating the thread in which the pause instruction is executed as paused, wherein the processor does not execute the thread indicated as paused, and wherein the operation to reassign the credits is executed in response to all the threads assigned credits either having no available credits or being in the paused state.

8. The article of manufacture of claim 7, wherein the operations further comprise:

initiating monitoring for an event in response to executing the pause instruction; and

indicating the thread having the paused status as not paused in response to detecting the event during the monitoring, wherein the thread whose status is changed from paused to not paused is enabled to be executed by the processor if the thread has available credits.

9. The article of manufacture of claim 8, wherein the pause instruction indicates a memory location which the thread on which the pause instruction is executed needs to access, wherein the event comprises a change to the indicated memory location.

10. A system, comprising:

a processor;

buffers accessible to the processor;

an operating system schedule executed by the processor to perform operations, the operations comprising;

setting credits in the buffers for a plurality of threads executed by the processor; and

code executed by the processor to perform operations, the operations comprising;

alternating among executing the threads having available credit;

decrementing the credit for one of the threads in response to executing the thread; and

initiating an operation to reassign credits to the threads in response to depleting all the thread credits.

11. The system of claim 10, wherein initiating the operation to reassign the credits comprises:

executing a replenish thread in response to depleting all the thread credits, wherein the replenish thread resets the thread credits; and

alternating among executing the threads having available credit in response to the replenish thread resetting the thread credits.

12. The system of claim 11, wherein when the threads have available credits, the replenish thread is indicated to not execute until all the thread credits are depleted, wherein the code is further executed by the processor to perform operations comprising:

indicating that the replenish thread is to execute in response to executing the replenish thread when all the thread credits are depleted; and

indicating that the replenish thread is not to execute until all the thread credits are depleted in response to resetting the thread credits.

13. The system of claim 10, wherein the buffers are included in the processor and wherein the operating system scheduler is further executed to perform operations comprising:

configuring the processor to execute the threads.

14. The system of claim 13, further comprising:

a main memory;

wherein the operating system scheduler is further executed to perform operations comprising;

allocating addresses in the main memory to the processor for the processor to use as virtual processor buffers to store status and the thread credits for designated threads, wherein the processor buffers for a first set of threads are maintained in the virtual processor buffers and the processor buffers for a second set of threads are maintained in the processor.

15. The system of claim 10, wherein the code is further executed by the processor to perform operations comprising:

executing a pause instruction when executing one thread; and

indicating the thread in which the pause instruction is executed as paused, wherein the processor does not execute the thread indicated as paused, and wherein the operation to reassign the credits is executed in response to all the threads assigned credits either having no available credits or being in the paused state.

16. A method, comprising:

setting credits for a plurality of threads executed by a processor;

alternating, by the processor, among executing the threads having available credit;

decrementing, by the processor, the credit for one of the threads in response to executing the thread; and

initiating an operation, by the processor, to reassign credits to the threads in response to depleting all the thread credits.

17. The method of claim 16, wherein initiating the operation to reassign the credits comprises:

executing, by the processor, a replenish thread in response to depleting all the thread credits, wherein the replenish thread resets the thread credits; and

alternating, by the processor, among executing the threads having available credit in response to the replenish thread resetting the thread credits.

18. The method of claim 17, wherein when the threads have available credits, the replenish thread is indicated to not execute until all the thread credits are depleted, further comprising:

indicating, by the processor, that the replenish thread is to execute in response to executing the replenish thread when all the thread credits are depleted; and

indicating, by the processor, that the replenish thread is not to execute until all the thread credits are depleted in response to resetting the thread credits.

19. The method of claim 16, wherein the thread credits are maintained in processor buffers, further comprising:

configuring, by an operating system scheduler, the processor to execute the threads and set the thread credits.

20. The method of claim 19, further comprising:

allocating, by the operating system scheduler, main memory addresses to the processor for the processor to use as virtual processor buffers to store status and the thread credits for designated threads, wherein the processor buffers for a first set of threads are maintained in the virtual processor buffers and the processor buffers for a second set of threads are maintained in the processor.

21. The method of claim 16, further comprising:

executing, by the processor, a pause instruction when executing one thread; and

indicating, by the processor, the thread in which the pause instruction is executed as paused, wherein the processor does not execute the thread indicated as paused, and wherein the operation to reassign the credits is executed in response to all the threads assigned credits either having no available credits or being in the paused state.