Assembly Comprising a Tachograph

• US 20080251577A1
• Filed: 08/30/2006
• Published: 10/16/2008
• Est. Priority Date: 09/12/2005
• Status: Active Grant

• Current Assignee: Continental Automotive GmbH (Continental AG)
• Original Assignee: VDO Automotive AG (Continental AG)
• Inventors: Salm, Michael, Kimmich, Franz, Lindinger, Andreas, Nather, Horst
• Granted Patent: US 7,905,394 B2
• Time in Patent Office: Days
• US Class Current: 235/377
• CPC Class Codes: G06K 13/08 Feeding or discharging cards

Abstract

An assembly has a tachograph and a data memory, in particular a data memory of a data card. The tachograph has an interface designed to exchange data between the tachograph and the data memory, logic function modules and at least one memory. In a method for operating the tachograph, as a result of high security requirements, the data transfer between the data memory and the tachograph is extremely time-intensive. At the start of the data transfer a virtual reproduction of the data memory is created in the memory of the tachograph and the logic function modules first have read and write access to the virtual reproduction in the memory. Data is then regularly written to the data memory of the data card by a write access to the memory, thus eliminating the differences between the virtual reproduction and the data memory.

Claims

1. An arrangement (1) having a tachograph (DTCO) and having a data store (13, 14), particularly a data store (13, 14) on a data card (4, 5), where the tachograph (DTCO) has an interface which is used for data interchange between the tachograph (DTCO) and the data store (13, 14), which tachograph (DTCO) has logic functional modules (FM) and at least one memory (DMEM), characterized

in that the logic functional modules (FM) are in a form such that at the start of the data transmission a virtual map (VI) (VI) of the data store (13, 14) is first of all created in the memory (DMEM) of the tachograph (DTCO), subsequent read and write access operations by the logic functional modules (FM) are first of all effected on the virtual map (VI) (VI) in the memory (DMEM), and a write operation is regularly effected by accessing the data store (13, 14) on the data card (4, 5), during which the differences between the virtual map (VI) (VI) and the data store (13, 14) are aligned.

2. The arrangement (1) as claimed in claim 1, characterized in that the regular read and write access is effected at periodic intervals of time, preferably every 12 hours.

3. The arrangement (1) as claimed in claim 1, characterized in that the regular read and write access is effected when a particular volume of data needs to be aligned between the virtual map (VI) and the data store (13, 14) on the basis of changes in the map.

4. The arrangement (1) as claimed in claim 1, characterized in that before the data store (13, 14) is separated from the tachograph (DTCO) the virtual map (VI) is aligned with the data store (13, 14).

5. The arrangement (1) as claimed in claim 1, characterized in that the data transmission between the data store (13, 14) and the tachograph (DTCO) takes place in encrypted form.

6. The arrangement (1) as claimed in claim 1, characterized in that the data store (13, 14) has a ring memory (RNG).

7. The arrangement (1) as claimed in claim 6, characterized in that the map (VI) of the ring memory (RNG′

) is in the form of a linear memory (DMEM), with a start address (1st) for the first entry and an end address (xst) for the last entry, where a stipulated addressing order (ADRSEQ) provides for the call to the end address (xst) to be followed by the call to the start address (1st).

8. The arrangement (1) as claimed in claim 1, characterized in that the virtual map (VI) of the data store (13, 14) maps the architecture of the data store (13, 14), and the data stored in the ring memory (RNG) are mapped in the map (VI) only in part.

9. The arrangement (1) as claimed in one of claims 6-8, characterized in that the virtual map (VI), following initial production, first of all maps only the data from the last entry block in the ring memory (RNG) of the data store (13, 14).

10. The arrangement (1) as claimed in one of claims 6-8, characterized in that the virtual map (VI) has at least one associated change pointer (p1, p2), namely the data store (13, 14) of the tachograph (DTCO) stores the location of the virtual map (VI) of the ring memory (RNG) at which the first change since the last alignment was made.

11. The arrangement (1) as claimed in claim 10, characterized in that a write operation in the virtual map (VI) extending from the end address (xst) to the start address (1st) of the map (VI) involves at least one first change pointer (p1) marking the location in front of the end address (xst) at which the changes after the last alignment have started and at least one second change pointer (p2) marks the location at which the write operation was continued after the end address (xst).

12. The arrangement (1) as claimed in claim 10 or 11, characterized in that the change pointers (p1) additionally also comprise information about the number (n1, n2) of bytes which have been stored in the ring memory (RNG′

) starting from the indicated location since the last alignment.

13. The arrangement (1) as claimed in one of the preceding claims, characterized in that single instances of the logic functional module (FM) effect read or write access operations on the map (VI) and in this context are coordinated by means of a central status variable (CDS).

14. The arrangement (1) as claimed in one of the preceding claims, characterized in that single instances of the logic functional modules (FM) effect write access operations on memory areas of the map (VI) and in this context are coordinated by means of a central status variable, the functional modules (FM) regularly requesting the status variable (CDS) and, when the status variable (CDS) has a particular value which is associated with the respective requesting functional module (FM), initiating queuing write operations.

15. The arrangement (1) as claimed in the preceding claim, characterized in that the logic functional modules (FM) which effect the write access operations on a memory area of the map (VI) change the status variable (CDS) following the conclusion of the queuing write access operations.

16. The arrangement (1) as claimed in the preceding claim, characterized in that the logic functional modules (FM) comprise a map status module (CDSA) which regularly retrieves the status variable (CDS) and allocates it a new value if another functional module (FM) has previously changed the value, which new value is associated with a particular functional module (FM) for the purpose of allocating the write access.

17. The arrangement (1) as claimed in one of the preceding claims, characterized in that the arrangement (1) comprises an electrical power supply (U) and is in a form such that, when the latter has failed, any other access to the data store (13, 14) is first of all preceded by identification data from the data store (13, 14) being compared with those from the virtual map of the data store (13, 14).

18. The arrangement (1) as claimed in the preceding claim, characterized in that it is in a form such that, in the event of a power failure, directly before entering a read or write operation from or to the data store (13, 14), when the power has returned, it first of all compares identification data from the data store (13, 14) with those from the virtual map of the data store (13, 14) and then starts the read or write operation.

19. The arrangement (1) as claimed in the preceding claim, characterized in that in the event of a power failure during a read operation from the data store (13, 14) the functional modules (FM) remain in the present state until the power returns and then continue the read operation from this state after identification data from the data store (13, 14) have first of all been compared with those from the virtual map (VI) of the data store (13, 14).

20. The arrangement (1) as claimed in one of the preceding claims, characterized in that in the event of a power failure directly following the conclusion of a read or write operation from or to the data store (13, 14), when the power has returned, identification data from the data store (13, 14) are first of all compared with those from the virtual map of the data store (13, 14).

21. A method for operating an arrangement (1) as claimed in one of the preceding claims.