SEMICONDUCTOR MODULE

• US 20080251903A1
• Filed: 04/16/2007
• Published: 10/16/2008
• Est. Priority Date: 04/16/2007
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Schiess, Klaus, Otremba, Ralf, Schloegel, Xaver, Tan Tien Lai, Charlie
• Granted Patent: US 7,759,777 B2
• Time in Patent Office: Days
• US Class Current: 257/678
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/06181 On opposite sides of the body
• CPC Class Codes: H01L 2224/20 Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 2224/24227 the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/92244 the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/142 Metallic substrates having insulating layers
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01047 Silver [Ag]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01327 : Intermediate phases, i.e. intermetallics compounds
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15165 : Monolayer substrate

Abstract

A module having a semiconductor chip with a first contact element on a first main surface and a second contact element on a second main surface is disclosed. The semiconductor chip is arranged on a carrier. An insulating layer and a wiring layer cover the second main surface and the carrier.

Claims

1. A module comprising:

a semiconductor chip having a first contact element on a first main surface and a second contact element on a second main surface;

a carrier, on which the semiconductor chip is arranged in such a way that the first main surface of the semiconductor chip faces the carrier; and

a first insulating layer and a wiring layer, which cover the second main surface of the semiconductor chip and the carrier.

2. The module of claim 1, comprising wherein a second insulating layer is arranged between the carrier and the wiring layer, the second insulating layer covering a lateral face of the semiconductor chip.

3. The module of claim 2, comprising wherein the carrier is connected to the wiring layer via a connecting line and the connecting line is led through the second insulating layer.

4. The module of claim 1, wherein the carrier has a depression, into which the semiconductor chip is introduced.

5. The module of claim 1, comprising wherein the first contact element is electrically conductively connected to the carrier.

6. The module of claim 5, comprising wherein the semiconductor chip is fixed to the carrier via an adhesion promoter and the adhesion promoter effects the electrically conductive connection.

7. The module of claim 1, comprising wherein the carrier is electrically conductive.

8. The module of claim 4, comprising wherein an insulating material is arranged between a lateral face of the semiconductor chip and the carrier.

9. The module of claim 4, comprising wherein there is a clearance between a lateral face of the semiconductor chip and the carrier.

10. The module of claim 1, wherein the first insulating layer comprises a film.

11. The module of claim 10, comprising wherein the film is photopatternable.

12. The module of claim 1, comprising wherein the wiring layer connects the second contact element, to an external contact element and the external contact element has a larger contact area than the second contact element.

13. The module of claim 1, comprising wherein the semiconductor chip is a power semiconductor chip.

14. A module comprising:

a semiconductor chip;

an electrically conductive carrier having a depression, into which the semiconductor chip is introduced; and

a wiring layer covering the semiconductor chip and the carrier.

15. The module of claim 14, comprising wherein there is a clearance between a lateral face of the semiconductor chip and the carrier.

16. The module of claim 14, comprising wherein an insulating film is applied to the semiconductor chip.

17. The module of claim 14, comprising wherein the semiconductor chip is a power semiconductor.

18. A module comprising:

a semiconductor chip;

a carrier having a depression, into which the semiconductor chip is introduced; and

a film covering the semiconductor chip and the carrier.

19. The module of claim 18, comprising wherein there is a clearance between a lateral face of the semiconductor chip and the carrier, the clearance being covered by the film.

20. The module of claim, comprising wherein a wiring layer is applied to the film.

21. A method comprising:

providing a semiconductor chip having a first contact element on a first main surface and a second contact element on a second main surface;

applying the semiconductor chip to a carrier in such a way that the first main surface of the semiconductor chip faces the carrier; and

applying a first insulating layer and a wiring layer to the second main surface of the semiconductor chip in such a way that the first insulating layer and the wiring layer cover the second main surface and the carrier.

22. The method of claim 21, comprising applying a second insulating layer to the carrier, the second insulating layer covering a lateral face of the semiconductor chip.

23. The method of claim 22, comprising leading a connecting line through the second insulating layer and the connecting line connects the carrier to the wiring layer.

24. The method of claim 21, comprising introducing a depression into the carrier and inserting the semiconductor chip into the depression.

25. The method of claim 21, comprising producing an electrically conductive connection between the first contact element and the carrier.

26. The method of claim 21, comprising, after the introduction of the semiconductor chip into the depression of the carrier, introducing an insulating material between a lateral face of the semiconductor chip and the carrier.

27. The method of claim 21, comprising wherein, after the introduction of the semiconductor chip into the depression of the carrier, a clearance remains between a lateral face of the semiconductor chip and the carrier and covering the clearance with a film as a first insulating layer.

28. The method of claim 27, comprising patterning the film.

29. The method of claim 21, comprising applying the wiring layer to the film.

30. The method of claim 21, comprising producing the wiring layer by thin-film technology.

31. The method of claim 21, comprising connecting the second contact element to an external contact element having a larger contact area than the second contact element.

32. A method comprising:

providing a plurality of semiconductor chips having in each case a first contact element on a first main surface and in each case a second contact element on a second main surface;

introducing the semiconductor chips into depressions of a carrier in such a way that the first main surfaces face the carrier;

applying a wiring layer is applied to the second main surfaces of the semiconductor chips after the introduction of the semiconductor chips into the depressions of the carrier; and

after the application of the wiring layer, singulating the semiconductor chips.

33. The method of claim 32, comprising producing the depressions of the carrier by embossing, deep-drawing, milling or electrochemical growth.