Thin film transistor, method of manufacturing the same, and flat panel display having the same

• US 20080258141A1
• Filed: 01/07/2008
• Published: 10/23/2008
• Est. Priority Date: 04/19/2007
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Sun-il, Song, I-hun, Park, Young-soo, Park, Jae-chul, Kim, Chang-jung
• Granted Patent: US 8,188,472 B2
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

A thin film transistor (TFT), a method of manufacturing the TFT, and a flat panel display comprising the TFT are provided. The TFT includes a gate, a gate insulating layer that contacts the gate, a channel layer that contacts the gate insulating layer and faces the gate with the gate insulating layer therebetween, a source that contacts an end of the channel layer; and a drain that contacts an other end of the channel layer, wherein the channel layer is an amorphous oxide semiconductor layer, and each of the source and the drain is a conductive oxide layer comprising an oxide semiconductor layer having a conductive impurity in the oxide semiconductor layer. A low resistance metal layer can further be included on the source and drain. A driving circuit of a unit pixel of a flat panel display includes the TFT.

Claims

1. A thin film transistor (TFT) comprising:

a gate;

a gate insulating layer that contacts the gate;

a channel layer that contacts the gate insulating layer and faces the gate with the gate insulating layer therebetween;

a source that contacts an end of the channel layer; and

a drain that contacts an other end of the channel layer,

wherein the channel layer is an amorphous oxide semiconductor layer, and each of the source and the drain is a conductive oxide layer comprising an oxide semiconductor layer having a conductive impurity in the oxide semiconductor layer.

2. The TFT of claim 1, further comprising a low resistance metal layer which is formed on the source and the drain.

3. The TFT of claim 1, wherein the oxide semiconductor layer of the source and drain has a basic composition identical to that of the amorphous oxide semiconductor layer of the channel layer.

4. The TFT of claim 1, wherein the oxide semiconductor layer of the source and drain has a basic composition different from that of the amorphous oxide semiconductor layer of the channel layer.

5. The TFT of claim 1, wherein the channel layer is formed of one selected from the ZnO group oxide semiconductor consisting of a ZnO layer, an IZO layer, and a G-I-Z-O layer.

6. The TFT of claim 1, wherein the source and the drain are formed of one selected from the group consisting of a G-I-Z-O layer, an ITO layer, an IZO layer, a ZnO layer, and a TiO layer.

7. The TFT of claim 1, wherein the conductive impurity is one selected from the group consisting of Al, In, B, and Si.

8. The TFT of claim 2, wherein the low resistance metal layer is a multiple layer.

9. The TFT of claim 1, wherein the gate is formed above or below the channel layer.

10. The TFT of claim 1, further comprising an etch stopper on the channel layer between the source and the drain.

11. The TFT of claim 1, wherein the gate is a single layer or a multiple layer.

12. The TFT of claim 11, wherein the gate comprises sequentially stacked a first MO layer, a metal layer, and a second Mo layer.

13. The TFT of claim 12, wherein the metal layer is an Al layer or an Nd layer.

36. A flat panel display in which a driving circuit of a unit pixel comprises two TFTs and one capacitor, wherein the TFT is the TFT of claim 1.

37. The flat panel display of claim 36, further comprising an etch stopper on a channel layer between a source and a drain.

38. The flat panel display of claim 36, further comprising a low resistance metal layer formed on the source and the drain.

39. The flat panel display of claim 36, wherein a basic composition of the oxide semiconductor layer of the source and the drain is identical to that of the amorphous oxide semiconductor layer of the channel layer.

40. The flat panel display of claim 36, wherein a basic composition of the oxide semiconductor layer of the source and the drain is different from that of the amorphous oxide semiconductor layer of the channel layer.

41. The flat panel display of claim 36, wherein the channel layer is formed of one selected from the ZnO group oxide semiconductor consisting of a ZnO layer, an IZO layer, and a G-I-Z-O layer.

42. The flat panel display of claim 36, wherein the source and the drain are formed of one selected from the group consisting of a G-I-Z-O layer, an ITO layer, an IZO layer, a ZnO layer, and a TiO layer.

43. The flat panel display of claim 36, wherein the conductive impurity is one selected from the group consisting of Al, B, Si, and In.

44. The flat panel display of claim 36, wherein the flat panel display is a liquid crystal display (LCD) or an organic light emitting diode (OLED) display.

14. A method of manufacturing a TFT comprising a gate, a channel layer, a source, and a drain, the method comprising:

forming the channel layer on a lower film; and

forming the source and the drain respectively contacting either ends of the channel layer on the lower film,

wherein the channel layer is formed of an amorphous oxide semiconductor layer, the source and the drain are formed of a conductive oxide layer, and the conductive oxide layer is formed by injecting a conductive impurity into an oxide semiconductor layer.

15. The method of claim 14, further comprising forming an etch stopper having a width smaller than that of the channel layer on the channel layer prior to forming the source and drain.

16. The method of claim 15, wherein the forming of the channel layer and the etch stopper further comprises:

(a) sequentially stacking the amorphous oxide semiconductor layer and an insulating layer that is to be patterned to the etch stopper on the lower film;

(b) sequentially patterning the insulating layer and the amorphous oxide semiconductor layer to a shape identical to the channel layer; and

(c) exposing the amorphous oxide semiconductor layer by removing a portion of the patterned insulating layer.

17. The method of claim 16, wherein the operations (b) and (c) are performed using a halftone mask or a slit photomask.

18. The method of claim 15, wherein a surface of the channel layer where the etch stopper is formed is treated with oxygen plasma prior to forming the etch stopper.

19. The method of claim 14, wherein the gate is formed of a single layer or a multiple layer.

20. The method of claim 14, further comprising forming of a low resistance metal layer on the source and the drain.

21. The method of claim 20, wherein the low resistance metal layer is formed of a single layer or a multiple layer.

22. The method of claim 14, wherein a surface of the lower film is washed prior to forming the channel layer.

23. The method of claim 15, wherein a surface of the channel layer where the etch stopper is formed is washed prior to forming the etch stopper.

24. The method of claim 22, wherein the washing is consecutively performed using isopropyl alcohol (IPA) and pure deionized (DI) water or using acetone, IPA, and pure DI water.

25. The method of claim 23, wherein the washing is consecutively performed using IPA and pure DI water or using acetone, IPA, and pure DI water.

26. The method of claim 14, wherein the conductive oxide layer is formed using a sputtering method under an oxygen-free atmosphere.

27. The method of claim 20, wherein the forming of the source, the drain, and the low resistance metal layer further comprises:

(a) forming an etch stopper having a width smaller than that of the channel layer on the channel layer;

(b) sequentially stacking the conductive oxide layer that cover the etch stopper and the channel layer, and the low resistance metal layer on the lower film;

(c) forming a mask that defines the source and the drain on the low resistance metal layer;

(d) sequentially removing the low resistance metal layer and the conductive oxide layer around the mask; and

(e) removing the mask.

28. The method of claim 14, wherein the conductive impurity is injected during the formation of the oxide semiconductor layer.

29. The method of claim 14, wherein the conductive impurity is injected into the oxide semiconductor layer using an ion injection process after the oxide semiconductor layer is formed.

30. The method of claim 14, wherein a basic composition of the oxide semiconductor layer of the source and the drain is identical to that of the amorphous oxide semiconductor layer of the channel layer.

31. The method of claim 14, wherein a basic composition of the oxide semiconductor layer of the source and drain is different from that of the amorphous oxide semiconductor layer of the channel layer.

32. The method of claim 14, wherein the channel layer is formed of one selected from the ZnO group oxide semiconductor consisting of a ZnO layer, an IZO layer, and a G-I-Z-O layer.

33. The method of claim 14, wherein the source and the drain are formed of one selected from the group consisting of a G-I-Z-O layer, an ITO layer, an IZO layer, a ZnO layer, and a TiO layer.

34. The TFT of claim 14, wherein the conductive impurity is one selected from the group consisting of Al, B, Si, and In.

35. The TFT of claim 14, wherein the gate is formed above or below the channel layer.