HETEROGENEOUS IMAGE PROCESSING SYSTEM

• US 20080260296A1
• Filed: 04/23/2007
• Published: 10/23/2008
• Est. Priority Date: 04/23/2007
• Status: Active Grant

• Current Assignee: Kyndryl Incorporated
• Original Assignee: International Business Machines Corporation
• Inventors: Kim, Moon J., Moulic, James R., Chung, William H., Sanuki, Toshiyuki
• Granted Patent: US 8,331,737 B2
• Time in Patent Office: Days
• US Class Current: 382/307
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining

Abstract

The present invention relates to machine vision computing environments, and more specifically relates to a system and method for selectively accelerating the execution of image processing applications using a multi-core processor system. To this extent, a multi-core processor system is generally defined as one that is multi-platform, and potentially distributed via a network or other connection. The invention provides a machine vision system and method for executing image processing applications referred to herein as an image co-processor that comprises (among other things) a plurality of multi-core processors (MCPs) that work to process multiple images in an accelerated fashion.

Claims

1. A heterogeneous image processing system, comprising:

an image co-processor comprising a plurality of multi-core processors (MCPs), the plurality of MCPs being configured to;

receive a plurality of images; and

process the plurality of images to determine associated image data.

2. The heterogeneous image processing system of claim 1, further comprising a control processor being configured to receive the image data from the image co-processor, and to determine control information for the plurality of images.

3. The heterogeneous image processing system of claim 2, further comprising:

a staging storage unit for storing the image data for use by the control processor; and

an archive storage unit for storing at least one of the image data or the control information.

4. The heterogeneous image processing system of claim 1, further comprising an input/output (I/O) processor, the I/O processor comprising:

a set of express peripheral component interconnects (PCIs);

a pure load balancer (PLB) coupled to the set of express PCIs; and

a network interface coupled to the PLB for interfacing with at least one legacy application.

5. The heterogeneous image processing system of claim 4, the I/O processor receiving the plurality of images from an image grabber, and providing the plurality of images to the image co-processor.

6. The heterogeneous image processing system of claim 1, the image co-processor further comprising:

a power processing element (PPE); and

an element interconnect bus (EIB) coupled to the PPE and the plurality of MCPs.

7. The heterogeneous image processing system of claim 1, the MCPs comprising accelerators that increase a rate of processing of the plurality of images.

8. The heterogeneous image processing system of claim 1, the heterogeneous image processing system being operable with multiple different computing platforms.

9. A heterogeneous image processing method, comprising:

receiving a plurality of images in an image co-processor, the image co-processor comprising a plurality of multi-core processors (MCPs);

processing the plurality of images with the plurality of MCPs to determine image data associated with the plurality of images; and

providing at least one of the image data or the plurality of images to a control processor to determine control information associated with the plurality of images.

10. The heterogeneous image processing method of claim 9, further comprising:

determining, the control information with the control processor.

11. The heterogeneous image processing method of claim 10, further comprising:

storing the image data in a staging storage unit for processing by the control processor to determine control information; and

storing at least one of the image data or the control information in an archive storage unit.

12. The heterogeneous image processing method of claim 9, further comprising:

receiving the plurality of images in an input/output (I/O) processor, the I/O processor comprising;

a set of express peripheral component interconnects (PCIs);

a pure load balancer (PLB) coupled to the set of express PCIs; and

a network interface coupled to the PLB for interfacing with at least one legacy application.

13. The heterogeneous image processing method of claim 12, the I/O processor receiving the plurality of images from an image grabber, and providing the plurality of images to the plurality of MCPs.

14. The heterogeneous image processing method of claim 9, the image co-processor further comprising:

a power processing element (PPE); and

an element interconnect bus (EIB) coupled to the PPE and the plurality of MCPs.

15. The heterogeneous image processing method of claim 9, the plurality of MCPs comprising accelerators that increase a rate of processing of the plurality of images.

16. The heterogeneous image processing method of claim 9, further comprising receiving the plurality of images in an image grabber from at least one image recording devices.

17. A program product stored on computer readable medium for heterogeneously processing an image, the computer readable medium comprising program code for causing a computer system to:

receive a plurality of images in an image co-processor, the image co-processor comprising a plurality of multi-core processors (MCPs);

process the plurality of images with the plurality of MCPs to determine image data associated with the plurality of images; and

provide at least one of the image data or the plurality of images to a control processor to determine control information associated with the plurality of images.

18. The program product of claim 17, the computer readable medium further comprising program code for causing the computer system to:

determine control information for the plurality of images with the control processor.

19. The program product of claim 18, the computer readable medium further comprising program code for causing the computer system to:

store the image data in a staging storage unit for processing by the control processor; and

store the at least one of the image data or the plurality of images in an archive storage unit.

20. The program product of claim 17, the computer readable medium further comprising program code for causing the computer system to:

receive the plurality of images in an input/output (I/O) processor, the I/O processor comprising;

a set of express peripheral component interconnects (PCIs);

a pure load balancer (PLB) coupled to the set of express PCIs; and

a network interface coupled to the PLB for interfacing with at least one legacy application.

21. The program product of claim 20, the I/O processor receiving the plurality of images from an image grabber, and providing the plurality of images to the plurality of MCPs.

22. The program product of claim 17, the image co-processor further comprising:

a power processing element (PPE); and

an element interconnect bus (EIB) coupled to the PPE and the plurality of MCPs.

23. The program product of claim 17, the MCPs comprising accelerators that increase a rate of processing of the plurality of images.

24. The program product of claim 17, further comprising receiving the plurality of images in an image grabber from at least one image recording devices.

25. A method for deploying a system for heterogeneously processing an image, comprising:

providing a computer infrastructure being operable to;

receive a plurality of images in an image co-processor, the image co-processor comprising a plurality of multi-core processors (MCPs); and

process the plurality of images with the plurality of MCPs to determine image data associated with the plurality of images.

26. A heterogeneous image processing system, comprising:

a plurality of image co-processors, each of the plurality of image co-processors comprising;

a set of image grabbers for receiving images from a set of image recording devices;

a set of input/output (I/O) processors coupled to the set of image grabbers;

a set of multi-core processors (MCPs) coupled to the set of I/O processors; and

a set of external data representation (XDR) modules coupled to the set of MCPs.

27. The heterogeneous image processing system of claim 26, further comprising a switch for coupling the plurality of image co-processors to a control processor.

28. The heterogeneous image processing system of claim 27, the switch being a gigabit Ethernet (GbE) switch.

29. The heterogeneous image processing system of claim 28, the control processor writing a library for the set of MCPs, and off-loading the library to the image co-processor at runtime.