THIN FILM TRANSISTOR ARRAY SUBSTRATE, METHOD OF MANUFACTURING SAME, AND DISPLAY DEVICE

• US 20080265254A1
• Filed: 04/22/2008
• Published: 10/30/2008
• Est. Priority Date: 04/27/2007
• Status: Abandoned Application

• Current Assignee: Mitsubishi Electric Corporation
• Original Assignee: Mitsubishi Electric Corporation
• Inventors: NISHIURA, Atsunori
• Application Number:
  US12/107,431
• Publication Number:
  US 20080265254A1
• Time in Patent Office: Days
• US Class Current: 257/59
• CPC Class Codes: G02F 1/136213 Storage capacitors associated with the pixel electrode
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors

Abstract

A thin film transistor array substrate in accordance with the present invention comprising a semiconductor layer formed over the substrate and having source/drain regions, a gate insulating film, a gate electrode, an interlayer insulating film, wiring electrodes connected to the source/drain regions, a protective film, a pixel electrode connected to the wiring electrode, a lower capacitor electrode formed with and extending from the semiconductor layer, a common line electrode formed from the same layer as the gate electrode and arranged in the opposed position to the lower capacitor electrode with the gate insulating film interposed therebetween, and an upper capacitor electrode arranged in the opposed position to the common line electrode with a dielectric film (protective film) having film thickness thinner than the interlayer insulating film interposed therebetween.

Claims

1. A thin film transistor array substrate comprising:

a semiconductor layer formed over a substrate and having source/drain regions;

a gate insulating film covering the semiconductor layer;

a gate electrode arranged in the opposed position to the channel region of the semiconductor layer with the gate insulating film interposed therebetween;

an interlayer insulating film covering the gate electrode;

a wiring electrode connected to the source/drain regions through a contact hole piercing through the interlayer insulating film and the gate insulating film;

a protective film covering the wiring electrode and the interlayer insulating film;

a pixel electrode connected to the wiring electrode through a through hole piercing through the protective film;

a lower capacitor electrode formed with and extending from the semiconductor layer;

a common line electrode formed from the same layer as the gate electrode and arranged in the opposed position to the lower capacitor electrode with the gate insulating film interposed therebetween; and

an upper capacitor electrode arranged in the opposed position to the common line electrode with a dielectric film having film thickness thinner than the interlayer insulating film interposed therebetween.

2. The thin film transistor array substrate according to claim 1, wherein

an area of the interlayer insulating film located above the common line electrode is removed to form an opening,

the protective film covers the opening and the sides of the interlayer insulating film that form an outline of the opening,

the dielectric film is formed from the protective film in the opening, and

the upper capacitor electrode arranged in the opposed position to the common line electrode with the dielectric film interposed therebetween is formed with and extending from the pixel electrode.

3. The thin film transistor array substrate according to claim 2, wherein

the common line electrode is formed from a Cr film, an alloy film containing Cr as the main ingredient, an Al film, or an alloy film containing Al as the main ingredient, and

the wiring electrode is formed from a Mo film, an alloy film containing Mo as the main ingredient.

4. The thin film transistor array substrate according to claim 1, wherein

a thin film portion having film thickness thinner than the interlayer insulating film located in an area distant from the common line electrode over the semiconductor layer is formed in an area of the interlayer insulating film located above the common line electrode,

the dielectric film is formed from the thin film portion of the interlayer insulating film, and

the upper capacitor electrode arranged in the opposed position to the common line electrode with the dielectric film interposed therebetween is formed with and extending from the wiring electrode to cover the thin film portion and the sides of the interlayer insulating film that form an outline of the thin film portion.

5. The thin film transistor array substrate according to claim 4, wherein

the interlayer insulating film comprises a first interlayer insulating film covering the gate electrode and the common line electrode, and a second interlayer insulating film formed on the first interlayer insulating film, and

the thin film portion is formed by removing the second interlayer insulating film in the area above the common line electrode.

6. The thin film transistor array substrate according to claim 4, wherein

the interlayer insulating film is formed from a single-layer interlayer insulating film covering the gate electrode and the common line electrode, and

the thin film portion is formed by removing the single-layer interlayer insulating film partially in the direction of thickness.

7. A display device comprising the thin film transistor array substrate of claim 1.

8. A method of manufacturing a thin film transistor array substrate, comprising:

a step for forming a semiconductor layer having source/drain regions, and a lower capacitor electrode extending from the semiconductor layer over a substrate;

a step for forming a gate insulating film covering the semiconductor layer and the lower capacitor electrode;

a step for forming a gate electrode arranged in the opposed position to the channel region of the semiconductor layer with the gate insulating film interposed therebetween, and a common line electrode arranged in the opposed position to the lower capacitor electrode with the gate insulating film interposed therebetween;

a step for forming an interlayer insulating film covering the gate electrode and the common line electrode;

a step for forming a contact hole with the source/drain regions being exposed and an opening with the common line electrode being exposed by etching the interlayer insulating film and the gate insulating film;

a step for forming a wiring electrode connected to the source/drain regions through the contact hole;

a step for forming a protective film having film thickness thinner than the interlayer insulating film so as to cover the wiring electrode, the interlayer insulating film, and the opening, and to have a through hole with a part of the wiring electrode being exposed; and

a step for forming a pixel electrode connected to the wiring electrode through the through hole and arranged in the opposed position to the common line electrode with the protective film interposed therebetween.

9. The method of manufacturing a thin film transistor array substrate according to claim 8, wherein

in the step for forming the gate electrode and the common line electrode, the gate electrode and the common line electrode are formed from a Cr film, an alloy film containing Cr as the main ingredient, an Al film, or an alloy film containing Al as the main ingredient, and

in the step for forming the wiring electrode, the wiring electrode is formed from a Mo film, an alloy film containing Mo as the main ingredient.

10. The method of manufacturing a thin film transistor array substrate according to claim 9, wherein

in the step for forming the wiring electrode, the wiring electrode is formed by dry-etching using mixed gas of SF₆ and O₂, or mixed gas of Cl₂ and O₂.

11. A method of manufacturing a thin film transistor array substrate, comprising:

a step for forming a semiconductor layer having source/drain regions, and a lower capacitor electrode extending from the semiconductor layer over a substrate;

a step for forming a gate insulating film covering the semiconductor layer and the lower capacitor electrode;

a step for forming a gate electrode arranged in the opposed position to the channel region of the semiconductor layer with the gate insulating interposed therebetween, and a common line electrode arranged in the opposed position to the lower capacitor electrode with the gate insulating film interposed therebetween;

a step for forming an interlayer insulating film covering the gate electrode and the common line electrode;

a step for forming a contact hole with the source/drain regions being exposed and a thin film portion having thinner film thickness in the interlayer insulating film above the common line electrode by etching the interlayer insulating film and the gate insulating film;

a step for forming a wiring electrode connected to the source/drain regions through the contact hole and arranged in the opposed position to the common line electrode with the thin film portion in the interlayer insulating film interposed therebetween;

a step for forming a protective film so as to cover the wiring electrode and the interlayer insulating film and to have a through hole with a part of the wiring electrode being exposed; and

a step for forming a pixel electrode connected to the wiring electrode through the through hole.

12. The method of manufacturing a thin film transistor array substrate according to claim 11, wherein the step for forming the contact hole and the thin film portion includes:

a step for etching the interlayer insulating film and the gate insulating film using a first resist pattern formed on the interlayer insulating film as a mask to form the contact hole; and

a step for etching the interlayer insulating film partially in the direction of thickness using a second resist pattern formed on the interlayer insulating film as a mask to form the thin film portion.

13. The method of manufacturing a thin film transistor array substrate according to claim 11, wherein the step for forming the contact hole and the thin film portion includes:

a step for forming a resist pattern having film thickness difference on the interlayer insulating film by multiple tone exposure;

a step for etching and removing a stacked film of the interlayer insulating film and the gate insulating film partially in the direction of thickness in the area for the contact hole using the resist pattern having the film thickness difference as a mask;

a step for ashing the resist pattern having the film thickness difference to remove the thin film part of the resist pattern; and

a step for etching the stacked film in the area for the contact hole using the resist pattern with the thin film part being removed as a mask to form the contact hole, and etching the interlayer insulating film partially in the direction of thickness in the area for the thin film portion to form the thin film portion.

14. The method of manufacturing a thin film transistor array substrate according to claim 11, wherein

in the step for forming the interlayer insulating film, a first interlayer insulating film covering the gate electrode and the common line electrode is formed, and then a second interlayer insulating film is formed on the first interlayer insulating film, and

in the step for forming the contact hole and the thin film portion, the thin film portion is formed by removing the second interlayer insulating film in the area above the common line electrode to expose the first interlayer insulating film.

15. The method of manufacturing a thin film transistor array substrate according to claim 14, wherein

in the step for forming the interlayer insulating film, a first interlayer insulating film is formed by a CVD using TEOS, and then a second interlayer insulating film is formed from a silicon nitride film, and

the step for forming the contact hole and the thin film portion includes:

a step for etching the interlayer insulating film and the gate insulating film using a first resist pattern formed on the interlayer insulating film as a mask to form the contact hole; and

a step for dry-etching the second interlayer insulating film with mixed gas of CF₄, CO, and Ar using a second resist pattern formed on the interlayer insulating film as a mask to form the thin film portion.