Semiconductor Package Having Through-Hole Via on Saw Streets Formed with Partial Saw

• US 20080274603A1
• Filed: 09/25/2007
• Published: 11/06/2008
• Est. Priority Date: 05/04/2007
• Status: Active Grant

• Current Assignee: JCET Semiconductor (Shaoxing) Co., Ltd.
• Original Assignee: Stats Chippac Limited
• Inventors: KUAN, Heap Hoe, DO, Byung Tai, CHUA, Linda Pei Ee
• Granted Patent: US 7,585,750 B2
• Time in Patent Office: Days
• US Class Current: 438/462
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48472 the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
• CPC Class Codes: H01L 2224/73259 Bump and HDI connectors
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06551 Conductive connections on the side of the device
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/3135 Double encapsulation or coating and encapsulation
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 25/03 : all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/18162 : of a chip with build-up interconnect
• CPC Class Codes: H01L 2924/19104 : on the semiconductor or solid-state device, i.e. passive-on-chip
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/19107 : off-chip wires
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/30105 : Capacitance

Abstract

A method of forming through-hole vias in a semiconductor wafer involves forming a semiconductor wafer with many die having contact pads disposed on each die. The semiconductor wafer has saw street guides between each die. A trench is formed in the saw streets. The trench extends partially but not completely through the wafer. The uncut portion of the saw street guides below the trench along a backside of the wafer maintains structural support for the semiconductor wafer. The trench is filled with organic material. Via holes are formed in the organic material. Traces are formed between the contact pads and via holes. Conductive material is deposited in the via holes to form metal vias. The uncut portion of the saw streets below the trench along the backside of the semiconductor wafer portion is removed. The semiconductor wafer is singulated along the saw street guides to separate the die.

Claims

1. A method of forming through-hole vias in a semiconductor wafer, comprising:

forming a semiconductor wafer having a plurality of die with contact pads disposed on a surface of each die, the semiconductor wafer having saw street guides between each die;

forming a trench in the saw street guides, the trench extending partially but not completely through the semiconductor wafer, the uncut portion of the saw street guides below the trench along a backside of the semiconductor wafer maintaining structural support for the semiconductor wafer;

filling the trench with organic material;

forming a plurality of via holes in the organic material;

forming traces between the contact pads and via holes;

depositing conductive material in the via holes to form metal vias;

removing the uncut portion of the saw street guide below the trench along the backside of the semiconductor wafer portion; and

singulating the semiconductor wafer along the saw street guides to separate the die into individual units.

2. The method of claim 1, wherein at least one metal via is formed between the contact pads on adjacent die.

3. The method of claim 2, wherein the semiconductor wafer is singulated through the at least one metal via to form metal vias electrically connected to the contact pads by the traces.

4. The method of claim 1, wherein two metal vias are formed side by side between the contact pads on adjacent die.

5. The method of claim 4, wherein the semiconductor wafer is singulated along the saw street guides between the two metal vias to form metal vias electrically connected to the contact pads by the traces.

6. The method of claim 1, wherein the trench is less than a width of the saw street guides.

7. The method of claim 1, wherein the trench is centered about the saw street guides.

8. The method of claim 1, wherein the die are stackable and connected by the metal vias when stacked.

9. A method of forming through-hole vias in a semiconductor wafer, comprising:

forming a semiconductor wafer having a plurality of die with contact pads disposed on a surface of each die, the semiconductor wafer having saw street guides between each die;

cutting a trench in the saw street guide, the trench extending only partially through the semiconductor wafer, the uncut portion of the saw street guides below the trench along a backside of the semiconductor wafer maintaining structural support for the semiconductor wafer;

forming a plurality of via holes in the saw streets adjacent to the contact pads;

depositing conductive material in the via holes to form metal vias;

electrically connecting the metal vias to the contact pads;

removing the uncut portion of the saw street guide below the trench along the backside of the semiconductor wafer portion; and

singulating the semiconductor wafer along the saw street guides to separate the die.

10. The method of claim 9, further including:

filling the trench with organic material after forming the via holes; and

forming traces between the contact pads and via holes.

11. The method of claim 10, wherein at least one metal via is formed between the contact pads on adjacent die.

12. The method of claim 11, wherein the semiconductor wafer is singulated through the at least one metal via to form metal vias electrically connected to the contact pads by the traces.

13. The method of claim 10, wherein two metal vias are formed side by side between the contact pads on adjacent die.

14. The method of claim 13, wherein the semiconductor wafer is singulated along the saw street guides between the two metal vias to form metal vias electrically connected to the contact pads by the traces.

15. A method of forming through-hole vias in a semiconductor wafer, comprising:

forming a semiconductor wafer having a plurality of die with contact pads disposed on a surface of each die, the semiconductor wafer having saw street guides between each die;

forming a trench in the saw street guide, the trench extending only partially through the semiconductor wafer;

forming metal vias in the trenches of the saw streets;

electrically connecting the metal vias to the contact pads;

removing the uncut portion of the saw street guide below the trench along the backside of the semiconductor wafer portion; and

singulating the semiconductor wafer along the saw street guides to separate the die.

16. The method of claim 15, further including:

filling the trench with organic material;

forming a plurality of via holes in the organic material;

forming traces between the contact pads and via holes; and

depositing conductive material in the via holes to form metal vias.

17. The method of claim 16, wherein at least one metal via is formed between the contact pads on adjacent die.

18. The method of claim 17, wherein the semiconductor wafer is singulated through the one metal via to form metal half-vias electrically connected to the contact pads by the traces.

19. The method of claim 16, wherein two metal vias are formed side by side between the contact pads on adjacent die.

20. The method of claim 19, wherein the semiconductor wafer is singulated along the saw street guides between the two metal vias to form metal vias electrically connected to the contact pads by the traces.

21. The method of claim 15, wherein the trench is less than a width of the saw street guides.

22. The method of claim 15, wherein the trench is centered about the saw street guides.

23. The method of claim 15, wherein the die are stackable and connected by the metal vias when stacked.