MULTI-PROCESSOR DEVICE

• US 20080282012A1
• Filed: 01/08/2008
• Published: 11/13/2008
• Est. Priority Date: 01/22/2007
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Inventors: ISHIMI, Koichi
• Granted Patent: US 8,200,878 B2
• Time in Patent Office: Days
• US Class Current: 710/306
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: G06F 1/3293 by switching to a less power-consuming processor, e.g. sub-CPU
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 13/4031 with arbitration
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: G06F 15/8007 single instruction multiple data [SIMD] multiprocessors
• CPC Class Codes: G06F 9/3887 controlled by a single instruction for multiple data lanes [SIMD]
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The present invention intends to provide a high-performance multi-processor device in which independent buses and external bus interfaces are provided for each group of processors of different architectures, if a single chip includes a plurality of multi-processor groups. A multi-processor device of the present invention comprises a plurality of processors including first and second groups of processors of different architectures such as CPUs, SIMD type super-parallel processors, and DSPs, a first bus which is a CPU bus to which the first processor group is coupled, a second bus which is an internal peripheral bus to which the second processor group is coupled, independent of the first bus, a first external bus interface to which the first bus is coupled, and a second external bus interface to which the second bus is coupled, over a single semiconductor chip.

Claims

1. A multi-processor device comprising, over a single semiconductor chip:

a plurality of processors including a first group of processors and a second group of processors;

a first bus to which the first group of processors is coupled;

a second bus to which the second group of processors is coupled;

a first external bus interface to which the first bus is coupled; and

a second external bus interface to which the second bus is coupled.

2. The multi-processor device according to claim 1, further comprising a bus bridge circuit that couples the first bus and the second bus.

3. The multi-processor device according to claim 1, further comprising a secondary cache that couples the first bus and the second bus to each other.

4. The multi-processor device according to claim 1, wherein the first group of processors and the second group of processors are disposed separately in a layout region including the first bus and the first group of processors and a layout region including the second bus and the second group of processors, over the semiconductor chip.

5. The multi-processor device according to claim 1, wherein the first external bus interface and the second external bus interface are disposed far apart from each other over the semiconductor chip.

6. The multi-processor device according to claim 1, further comprising a secondary cache located between the first bus and the first external bus interface or between the second bus and the second external bus interface.

7. The multi-processor device according to claim 1, wherein the first group of processors or the second group of processors contains same-type processors in SMP structure.

8. The multi-processor device according to claim 7, wherein the processors in SMP structure contained in the first group of processors and the processors in SMP structure contained in the second group of processors are processors of different types.

9. The multi-processor device according to claim 8, wherein the processors of different types are CPUs of different architectures

10. The multi-processor device according to claim 8, wherein the processors of different types are CPUs and matrix type processors.

11. The multi-processor device according to claim 8, wherein the processors of different types are CPUs and DSPs.

12. The multi-processor device according to claim 10, wherein a CPU of another architecture is also coupled to the bus to which the matrix type processors are coupled or to which the DSPs are coupled.

13. The multi-processor device according to claim 1, wherein the first group of processors and the second group of processors are controlled with separate clocks and differ in frequency or phase.

14. The multi-processor device according to claim 1, wherein, of the first group of processors and the second group of processors, the region of the processor group controlled with a high frequency clock has closely spaced wiring of voltage supply lines and the region of the processor group controlled with a low frequency clock has sparse wiring of voltage supply lines.

15. The multi-processor device according to claim 1, wherein, of the first group of processors and the second group of processors, the region of the processor group controlled with a high frequency clock has a larger number of voltage supply terminals and the region of the processor group controlled with a low frequency clock has a smaller number of voltage supply terminals.

16. The multi-processor device according to claim 1, wherein, the CPU region and the external bus interface of the processor group which is controlled with a high frequency clock, of the first group of processors and the second group of processors, are disposed far apart from each other over the semiconductor chip.

17. The multi-processor device according to claim 16, wherein a high rate clock is supplied to the CPUs in the processor group controlled with the high frequency clock, and a clock for the bus to which the external bus interface and the processors for data processing are coupled is generated by gating a part of the clock.

18. The multi-processor device according to claim 1, wherein the first group of processors and the second group of processors operate on different OSs.