ADAPTIVE MECHANISMS AND METHODS FOR SUPPLYING VOLATILE DATA COPIES IN MULTIPROCESSOR SYSTEMS

• US 20080282032A1
• Filed: 07/18/2006
• Published: 11/13/2008
• Est. Priority Date: 07/18/2006
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Shen, Xiaowei, Sawdey, Aaron Christoph, Ng, Man Cheuk
• Granted Patent: US 7,478,197 B2
• Time in Patent Office: Days
• US Class Current: 711/117
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/0831 using a bus scheme, e.g. with bus monitoring or watching means
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/507 using speculative control

Abstract

In a computer system with a memory hierarchy, when a high-level cache supplies a data copy to a low-level cache, the shared copy can be either volatile or non-volatile. When the data copy is later replaced from the low-level cache, if the data copy is non-volatile, it needs to be written back to the high-level cache; otherwise it can be simply flushed from the low-level cache. The high-level cache can employ a volatile-prediction mechanism that adaptively determines whether a volatile copy or a non-volatile copy should be supplied when the high-level cache needs to send data to the low-level cache. An exemplary volatile-prediction mechanism suggests use of a non-volatile copy if the cache line has been accessed consecutively by the low-level cache. Further, the low-level cache can employ a volatile-promotion mechanism that adaptively changes a data copy from volatile to non-volatile according to some promotion policy, or changes a data copy from non-volatile to volatile according to some demotion policy.

Claims

1. A system for adaptively supplying data copies between a high level cache memory and a low level cache memory in a computing environment, comprising:

a cache memory having a high level cache memory arranged to store a plurality of high level cache lines and a low level cache memory connected to the high level cache memory by an interconnection, wherein the low level cache memory comprises a plurality of memory components, each of the memory components storing a plurality of low level cache lines, wherein each of the memory components has a unique identifier;

a prediction mechanism arranged to maintain an access flag for each of said plurality of high level cache lines, wherein the prediction mechanism updates the access flag in response to the low-level cache accessing the high level cache line, the update based on the identifier of the memory components of the low level cache performing the access, and wherein the prediction mechanism outputs a volatility flag associated with the accessed high level cache line, the volatility flag having a range of values including a volatile value and a non-volatile value, wherein the value is set based on the updated access flag and on said access flag prior to the update,

wherein the low level cache memory is arranged to receive and store, as a data copy in one of the low level cache lines, a high level cache line accessed in the high level cache memory, and to store, in a manner associated with the data copy, the volatility flag output by the prediction mechanism associated with the accessed high level cache line, and

wherein the low level cache memory is arranged to perform selective write-back of data copies stored in the low level cache lines, back into the high level cache memory, based on the value of the volatility flags associated with the copies, the selective write-back writing the data copy back into the high level cache memory if the volatility flag has the non-volatile value and the selective write-back not writing the data copy back into the high level cache memory if the volatility flag has the volatile flag value.

5. The system of claim 1, wherein the low-level cache memory is an L2 (Level 2) cache, and the high-level cache memory is an L3 (Level 3) cache.

6. The system of claim 1, wherein the prediction mechanism is arranged to compare the identifiers of the memory components accessing the high level cache with the access flags associated with the accessed high level cache line and, based on the comparison, to determine if the same memory component has consecutively accessed the same high level cache line, and is arranged to output the volatility flag for the data copy at the non-volatile flag value only if the comparison determines said consecutive access.

7. The system of claim 1, wherein at least one of the memory components of the low level cache memory is arranged local to the high level cache memory and at least one of the memory components of the low level cache memory is arranged remote from the high level cache memory, and wherein the prediction mechanism is arranged to compare the identifiers of the memory components accessing the high level cache with the access flags associated with the accessed high level cache line and, based on the comparison, to determine if any of the remote memory components has consecutively accessed the same high level cache line, and is arranged to output the volatility flag for the data copy at the non-volatile flag value only if the comparison determines said consecutive access.

2-4. -4. (canceled)

8-20. -20. (canceled)