METHOD AND STRUCTURE FOR FORMING STRAINED SI FOR CMOS DEVICES

• US 20080283824A1
• Filed: 07/15/2008
• Published: 11/20/2008
• Est. Priority Date: 11/05/2003
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Yang, Haining S., Zhang, Ying, STEEGEN, An L.
• Granted Patent: US 7,700,951 B2
• Time in Patent Office: Days
• US Class Current: 257/24
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/0243 Surface structure
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02658 Pretreatments cleaning in general H01L21/02041
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/2658 of a molecular ion, e.g. decaborane
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/76232 of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls H01L21/76229 takes precedence
• CPC Class Codes: H01L 21/76283 Lateral isolation by refilling of trenches with dielectric material
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66575 where the source and drain or source and drain extensions are self-aligned to the sides of the gate H01L29/66606 takes precedence
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7842 means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate variation of the composition of the channel H01L29/1054
• CPC Class Codes: H01L 29/7846 the means being located in the lateral device isolation region, e.g. STI
• CPC Class Codes: H01L 29/7849 : the means being provided under the channel

Abstract

A semiconductor device includes a semiconductor substrate having at least one gap, extending under a portion of the semiconductor substrate. A gate stack is on the semiconductor substrate. A strain layer is formed in at least a portion of the at least one gap. The strain layer is formed only under at least one of a source region and a drain region of the semiconductor device.

Claims

1. A semiconductor device, comprising:

a semiconductor substrate having at least one gap, extending under a portion of the semiconductor substrate;

a gate stack on the semiconductor substrate; and

a strain layer formed in at least a portion of the at least one gap before the gate stack is formed on the semiconductor substrate,

wherein the at least one gap is formed by doping a portion of the semiconductor substrate and then etching the doped portion of the semiconductor substrate.

2. The device of claim 1, wherein the gap is formed prior to forming the gate stack.

3. The device of claim 1, wherein the semiconductor device is doped with at least one of Ge, As, B, In and Sb.

4. A semiconductor device, comprising:

a semiconductor substrate;

a strain layer arranged in a gap formed in the semiconductor substrate such that at least a portion of the semiconductor substrate extends over the gap; and

one of;

a gate stack formed on the semiconductor substrate after the strain layer is arranged in the gap; and

source and drain regions formed in upper portions of the semiconductor substrate after the strain layer is arranged in the gap.

5. The device of claim 4, wherein the at least one gap is formed by doping a portion of the semiconductor substrate and then etching the doped portion of the semiconductor substrate.

6. The device of claim 4, wherein the strain layer is formed directly under a channel of the semiconductor device.

7. A semiconductor device, comprising:

a semiconductor substrate having at least one gap, extending under a portion of the semiconductor substrate;

a strain layer formed in at least a portion of the at least one gap,

wherein the strain layer is formed only under at least one of a source region and a drain region of the semiconductor device.

8. The device of claim 7, wherein the semiconductor device is a p-type device.

9. The device of claim 7, wherein the strain layer is made of at least one of silicon germanium or silicon carbide.

10. The device of claim 7, wherein the strain layer is between a surface of an upper portion of the semiconductor substrate which faces a surface of a lower portion of the semiconductor substrate.

11. The device of claim 7, wherein the strain layer has a thickness of about 1000 Angstroms to about 5000 Angstroms.

12. The device of claim 11, wherein a thickness of the channel is about 30 Angstroms to about 200 Angstroms.

13. The device of claim 7, wherein the strain layer is formed under both the source region and the drain region of the semiconductor device.

14. The device of claim 7, wherein the gap has a first width along an upper surface of the semiconductor substrate and a second width below the upper surface of the semiconductor substrate and the second width is larger than the first width.

15. The device of claim 7, wherein compressive stresses of about 100 MPa to about 3 GPa exist within the channel of the device.

16. The device of claim 7, wherein the strain layer is at least one of SiGe, Si₃N₄, SiO₂ and SiO_xN_y.

17. The device of claim 7, wherein the at least one gap is a tunnel gap.

18. The device of claim 7, wherein the strain layer is formed between upper and lower portions of the semiconductor substrate.