Semiconductor device and method for fabricating the same

• US 20080284026A1
• Filed: 11/14/2007
• Published: 11/20/2008
• Est. Priority Date: 09/26/2003
• Status: Active Grant

• Current Assignee: RPX Corporation
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Hashimoto, Shin, Mimura, Tadaaki
• Granted Patent: US 7,741,207 B2
• Time in Patent Office: Days
• US Class Current: 257/758
• CPC Class Codes: H01L 2224/02166 Collar structures
• CPC Class Codes: H01L 2224/05093 of a plurality of vias
• CPC Class Codes: H01L 2224/05096 Uniform arrangement, i.e. array
• CPC Class Codes: H01L 2224/05556 in side view
• CPC Class Codes: H01L 2224/05558 conformal layer on a patterned surface
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/53228 the principal metal being copper
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 Silicon [Si]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01045 Rhodium [Rh]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]

Abstract

A semiconductor device comprises a first insulating film formed on a semiconductor substrate, a first metal pattern formed on the first insulating film, a second insulating film formed on the first metal pattern, a second metal pattern formed on the second insulating film, and a third metal pattern formed in the second insulating film and connecting between the first metal pattern and the second metal pattern. The third metal pattern is a single continuous structure, and the principal orientation axes of crystals of a metal constituting the third metal pattern are parallel to the principal surface of the semiconductor substrate.

Claims

1-56. -56. (canceled)

57. A method for fabricating a semiconductor device, said method comprising the steps of:

forming a first insulating film on a semiconductor substrate;

forming a first metal layer on the first insulating film;

patterning the first metal layer to form at least one first interconnect and a first pad;

forming a second insulating film on the first interconnect and the first pad;

forming, in the second insulating film, at least one hole-like first opening exposing the first interconnect and a trench-like second opening exposing the first pad;

in a common step, filling the first opening with a metal to form at least one first via connected to the first interconnect and filling the second opening with the metal to form a network via connected to the first pad;

forming a second metal layer on the second insulating film, the first via and the network via; and

patterning the second metal layer to form at least one second interconnect connected to the first via and a second pad connected to the network via,

wherein the network via is a single continuous structure having a honeycomb structure.

58. The method for fabricating a semiconductor device of claim 57, wherein

at least one third interconnect is formed below the first pad so as to be electrically isolated from the first pad through the first insulating film, and

the first pad is different from the third interconnect in electrical potential.

59. The method for fabricating a semiconductor device of claim 57, wherein

at least one fourth interconnect is formed below the first pad so as to be electrically connected to the first pad with the first insulating film interposed therebetween, and

the first pad is electrically connected to the fourth interconnect through a second via formed in the first insulating film.

60. The method for fabricating a semiconductor device of claim 57, wherein the first pad is formed to have a larger area than the second pad.

61. The method for fabricating a semiconductor device of claim 57, wherein

in plan configuration, the proportion of the network via to the region of the semiconductor device in which the second metal pattern is formed is 50% or more.

62. The method for fabricating a semiconductor device of claim 57, wherein the metal constituting the first metal pattern is aluminum or copper.

63. The semiconductor device of claim 57, wherein the metal constituting the second metal pattern is aluminum or copper.

64. The semiconductor device of claim 57, wherein the first via and the network via is made of tungsten or copper.

65. The method for fabricating a semiconductor device of claim 57, wherein the principal orientation axes of crystals of a metal constituting the network via are parallel to the principal surface of the semiconductor substrate.

66. The method for fabricating a semiconductor device of claim 65, wherein the distribution of orientations of the principal orientation axes of crystals of the metal constituting the network via is substantially uniform in a plane parallel to the principal surface of the semiconductor substrate.

67. The method for fabricating a semiconductor device of claim 66, wherein the metal constituting the network via has a body-centered cubic structure, and

the principal orientation axes of crystals of the metal constituting the network via are <

110>

axes.