SEMICONDUCTOR PACKAGES WITH ENHANCED JOINT RELIABILITY AND METHODS OF FABRICATING THE SAME

• US 20080290492A1
• Filed: 05/19/2008
• Published: 11/27/2008
• Est. Priority Date: 05/22/2007
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: JANG, Dong-Hyeon, CHUNG, Hyun-Soo, KIM, Nam-Seog, KANG, Sun-Won
• Granted Patent: US 7,598,607 B2
• Time in Patent Office: Days
• US Class Current: 257/686
• CPC Class Codes: H01L 2224/24226 the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/82039 using a laser
• CPC Class Codes: H01L 2224/82047 by mechanical means, e.g. severing, pressing, stamping
• CPC Class Codes: H01L 2224/92244 the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2225/1035 the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 25/105 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01038 Strontium [Sr]
• CPC Class Codes: H01L 2924/01047 Silver [Ag]
• CPC Class Codes: H01L 2924/01074 Tungsten [W]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15331 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/351 : Thermal stress

Abstract

Provided is a semiconductor package with enhanced joint reliability and methods of fabricating the same. The method includes: forming package units including a semiconductor chip interposed between a bottom layer and a top layer; and sequentially stacking the package units on a substrate. The bottom layer and the top layer are formed of a material having a lower modulus than the semiconductor chip. The semiconductor package includes: at least one package unit disposed on a substrate, the package unit including a semiconductor chip having a pad, a bottom layer and a top layer substantially surrounding the semiconductor chip, and a redistribution structure overlying the top layer. The redistribution structure is electrically connected to the pad.

Claims

1. A semiconductor package comprising:

a substrate; and

at least one package unit disposed on the substrate, the package unit including;

a semiconductor chip having a pad;

a bottom layer disposed below the semiconductor chip;

a top layer disposed on the semiconductor chip, the bottom layer and the top layer substantially surrounding the semiconductor chip; and

a redistribution structure overlying the top layer, the redistribution structure electrically connected to the pad,

wherein the top layer and the bottom layer each comprise a material having a lower modulus than the redistribution structure and the semiconductor chip.

2. The semiconductor package of claim 1, wherein the top layer and the bottom layer each comprise a material having a modulus between about 10 MPa and about 1 GPa.

3. The semiconductor package of claim 1, wherein the bottom layer and the top layer comprise at least one of silicone compounds, rubber compounds, photosensitive resin compounds, and synthetic resin compounds.

4. The semiconductor package of claim 1, wherein the bottom layer and the top layer have a thickness between about 10 μ

m and about 1000 μ

m.

5. The semiconductor package of claim 1, wherein the semiconductor chip has a thickness between about 10 μ

m and about 100 μ

m.

6. The semiconductor package of claim 1, wherein the redistribution structure is extended from the pad and covers an inner wall of a via hole that penetrates the top layer and the bottom layer.

7. The semiconductor package of claim 6, wherein the at least one package unit comprises a plurality of package units sequentially stacked on the substrate and each of the package units comprises a connecting element disposed in the via hole, and wherein the connecting elements of adjacent ones of the plurality of package units electrically connect the redistribution structures of the adjacent package units.

8. The semiconductor package of claim 7, further comprising a substrate connecting element electrically connecting the connecting elements of the package units to a substrate pad on the substrate.

9. The semiconductor package of claim 7, wherein the connecting elements of package units stacked farther from the substrate have a melting point less than melting points of connecting elements of package units stacked closer to the substrate.

10. The semiconductor package of claim 7, wherein the plurality of package units are sequentially stacked on the substrate such that the top layer of each of the package units is farther from the substrate than the bottom layer.

11. The semiconductor package of claim 7, wherein the plurality of package units are sequentially stacked on the substrate such that the bottom layer of each of the package units is farther from the substrate than the top layer.

12. The semiconductor package of claim 7, wherein at least one of the semiconductor chips is different from at least one other of the semiconductor chips in one or more of size, shape, and function.

13. The semiconductor package of claim 1, wherein the top layer and the bottom layer each comprise a different material.

14. The semiconductor package of claim 1, wherein the top layer and the bottom layer comprise the same material.