APPARATUS AND METHOD FOR PREVENTING CURRENT LEAKAGE WHEN A LOW VOLTAGE DOMAIN IS POWERED DOWN

• US 20080290935A1
• Filed: 05/24/2007
• Published: 11/27/2008
• Est. Priority Date: 05/24/2007
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Yang, Ge, Young, Charles Chew-Yuen, Lin, Hwong-Kwo
• Granted Patent: US 7,583,126 B2
• Time in Patent Office: Days
• US Class Current: 327/544
• CPC Class Codes: H03K 3/356104 using complementary field-effect transistors H03K3/35625 takes precedence

Abstract

An apparatus and method are provided for preventing a current leakage or direct current when a low voltage domain is powered down. Included is a voltage transition circuit connected between a low voltage domain and a high voltage domain. Such voltage transition circuit includes a circuit component for preventing a current leakage when the low voltage domain is powered down.

Claims

1. An apparatus, comprising:

a voltage transition circuit connected between a low voltage domain and a high voltage domain, the voltage transition circuit including circuit component for preventing a current leakage or direct current when the low voltage domain is powered down.

2. The apparatus of claim 1, wherein the low voltage domain and the high voltage domain are components of a processor.

3. The apparatus of claim 2, wherein the processor includes a graphics processor.

4. The apparatus of claim 1, wherein the low voltage domain is connected to a single rail input.

5. The apparatus of claim 4, wherein the voltage transition circuit is connected to the single rail input to convert a voltage of the low voltage domain received via the single rail input to a voltage of the high voltage domain.

6. The apparatus of claim 1, wherein the voltage transition circuit includes an input-falling-transition circuit, the input-falling-transition circuit comprising:

a p-type transistor; and

an n-type transistor having a drain connected to a drain of the p-type transistor at a contact point, a source connected to the single-rail input, the p-type transistor having a source connected to a VDDH voltage of the high voltage domain.

7. The apparatus of claim 6, wherein the n-type transistor has a gate connected to a power down input.

8. The apparatus of claim 1, wherein the voltage-transition circuit includes an input-rising-transition circuit, the input-rising-transition circuit comprising:

a first n-type transistor having a gate connected to a single-rail input, the first n-type transistor having a source connected to a ground voltage, and a drain connected to an output contact point, the output contact point being connected to a gate of a first p-type transistor of an input-falling-transition circuit; and

a second p-type transistor having a drain connected to the output contact point and a gate connected to a contact point of the input-falling-transition circuit.

9. The apparatus of claim 8, wherein the input-rising-transition circuit has a third p-type transistor connected in series with the second p-type transistor, the third p-type transistor having a drain connected to a source of the second p-type transistor and a gate connected to the single-rail input.

10. The apparatus of claim 9, wherein the circuit component comprises:

a second n-type transistor having a gate connected a power down input, a source connected to the ground voltage, and a drain connected to the output contact point.

11. The apparatus of claim 9, wherein the circuit component comprises:

a fourth p-type transistor having a gate connected a power down input, a source connected to the drain of the third p-type transistor, and a drain connected to a VDDH voltage of the high voltage domain.

12. The apparatus of claim 8, wherein the output contact includes an inverter.

13. The apparatus of claim 1, wherein the circuit component is adapted for preventing a direct current when the low voltage domain is powered down.

14. The apparatus of claim 1, wherein the voltage transition circuit is a component of a processor coupled to memory via a bus.

15. A method, comprising;

receiving at a voltage transition circuit a power supply voltage from a low voltage domain;

converting the power supply voltage from the low voltage domain to a high voltage domain; and

preventing a current leakage or direct current when the low voltage domain is powered down.

16. The method of claim 15, wherein the low voltage domain and the high voltage domain are components of a processor.

17. The method of claim 16, wherein the processor includes a graphics processor.

18. The method of claim 15, wherein the low voltage domain is connected to a single rail input.

19. The method of claim 18, wherein the voltage transition circuit is connected to the single rail input to convert a voltage of the low voltage domain received via the single rail input to a voltage of the high voltage domain.

20. A system, comprising:

means for receiving at a voltage transition circuit a power supply voltage from a low voltage domain;

means for converting the power supply voltage from the low voltage domain to a high voltage domain; and

means for preventing a current leakage or direct current when the low voltage domain is powered down.