CURRENT/VOLTAGE MODE IMAGE SENSOR WITH SWITCHLESS ACTIVE PIXELS

• US 20080291309A1
• Filed: 05/25/2007
• Published: 11/27/2008
• Est. Priority Date: 05/25/2007
• Status: Active Grant

• Current Assignee: Trustees Of The University Of Pennsylvania (University of Pennsylvania)
• Original Assignee: Trustees Of The University Of Pennsylvania (University of Pennsylvania)
• Inventors: Yang, Zheng, Gruev, Viktor, Van der Spiegel, Jan
• Granted Patent: US 7,924,332 B2
• Time in Patent Office: Days
• US Class Current: 348/308
• CPC Class Codes: H04N 25/677 for reducing the column or line fixed pattern noise
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array
• CPC Class Codes: H04N 25/766 comprising control or output lines used for a plurality of functions, e.g. for pixel output, driving, reset or power
• CPC Class Codes: H04N 25/778 comprising amplifiers shared between a plurality of pixels, i.e. at least one part of the amplifier must be on the sensor array itself

Abstract

A voltage and current mode active pixel sensor for high resolution imaging is presented. The photo pixel is composed of a photodiode and two transistors: reset and transconductance amplifier transistor. The switch transistor is moved outside the pixel, allowing for lower pixel pitch and increased linearity of the output photocurrent. The reset and amplifier (readout) transistors may also be shared among adjacent pixels by the introduction of transfer switches between the photodiodes and the source of the reset transistor and the gate of the readout transistor. The switch transistor outside the pixels provides biasing voltages or currents to the readout transistors to selectively turn them on when readout of the corresponding photodiode is desired and turns the readout transistor off when the corresponding photodiode is not to be read out. The increased linearity of the image sensor has greatly reduced spatial variations across the image after correlated double sampling and the column fix pattern noise is greatly improved.

Claims

1. An image sensor comprising:

a biasing circuit; and

a pixel array, each pixel in the pixel array comprising a photodiode, a reset transistor, and a readout transistor,

wherein the reset transistor controls operation of the photodiode and the gate voltage of the readout transistor, and

wherein the readout transistor is configured to provide an output proportional to a voltage or current output of the photodiode, where the drains of readout transistors of each pixel in the same row or column are connected directly together and to said biasing circuit and/or the sources of readout transistors of each pixel in the same row or column are connected directly together and to said biasing circuit, and the gate of said readout transistor is connected to said biasing circuit via the reset transistor, wherein voltages or currents from said biasing circuit are applied to said readout transistor to turn on said readout transistor when an output of the photodiode is to be read out and to turn off said readout transistor when an output of the photodiode is not to be read out.

2. The image sensor of claim 1, wherein the photodiode is connected between ground or a predetermined voltage and a source of said reset transistor and a drain of said reset transistor is connected to a reset voltage, or the photodiode is connected between a voltage reference and a drain of said reset transistor and a source of said reset transistor is connected to said reset voltage.

3. The image sensor of claim 2, wherein a gate of said readout transistor is connected to said source of said reset transistor.

4. The image sensor of claim 3, wherein the drains of each readout transistor in a row are connected directly to each other in a direction parallel to said row and the sources of each readout transistor in a column are connected directly to each other in a direction perpendicular to said row.

5. The image sensor of claim 1, wherein the biasing circuit comprises a current conveyor circuit for each row or column of said pixel array, said current conveyor circuit pinning an input line thereto to a reference voltage.

6. The image sensor of claim 5, wherein each current conveyor circuit comprises an operational amplifier connected to said reference voltage at a first input and to a row or column of connected drains or sources for the readout transistors of each pixel in said row or column of said pixel array.

7. The image sensor of claim 5, further comprising a row or column addressing switch connected to an output of each current conveyor circuit for selecting the corresponding row or column for read out.

8. The image sensor of claim 7, further comprising a correlated double sampling unit connected to each said addressing switch for sampling and storing an input photocurrent from one or more of said pixels.

9. The image sensor of claim 7, further comprising a column or row addressing switch connected to each column or row of connected sources or drains for the readout transistors of each pixel in each column or row of said pixel array.

10. The image sensor of claim 1, wherein the biasing circuit comprises a global current conveyor circuit for said pixel array, said current conveyor circuit pinning an input line thereto to a reference voltage.

11. The image sensor of claim 1, wherein the photodiode is connected between ground or predetermined voltage and a transfer switch transistor to a source or drain of said reset transistor, wherein a drain or source of said reset transistor is connected to a reset voltage and said reset transistor is shared by a plurality of pixels in said pixel array.

12. The image sensor of claim 11, wherein a gate of said readout transistor is connected to said source or drain of said reset transistor and said readout transistor is shared by said plurality of pixels in said pixel array, wherein properly biasing the gate of the said transfer switch transistor for a pixel connects the photodiode for said pixel to the gate of the readout transistor.

13. The image sensor of claim 12, wherein said plurality of pixels is 4 whereby each pixel utilizes an equivalent of 1.5 transistors.

14. The image sensor of claim 11, wherein a gate of the transfer switch transistor of each pixel in a row or column is controlled by an addressing switch outside the pixel array that selectively connects the transfer switch transistors of said row or column to said biasing circuit so as to select the pixels containing each of said transfer switch transistors.

15. The image sensor of claim 14, wherein the drain or source of the reset transistor of said plurality of pixels is connected to the reset transistors of other pluralities of pixels in common rows or columns of said pixel array, the drains or sources of said connected reset transistors being further selectively connected to the biasing circuit.

16. The image sensor of claim 12, wherein the sources or drains of each readout transistor in a column or row of pixels are connected to each other and to ground or suitable voltage and the drains or sources of each readout transistor in said column or row of pixels are connected to each other directly and to said biasing circuit through an addressing switch.

17. The image sensor of claim 15, wherein said biasing circuit comprises a current conveyor that pins an input line thereto to a reference voltage.

18. The image sensor of claim 17, further comprising a correlated double sampling unit connected to an output of said current conveyor sampling and storing an input photocurrent from one or more of said pixels.

19. The image sensor of claim 12, wherein the drains of each readout transistor in a column or row of pixels are connected directly to each other and to a reference voltage and the sources of each readout transistor in said column or row of pixels are connected to the biasing circuit through an addressing switch.

20. The image sensor of claim 19, wherein said biasing circuit comprises a bias current source.

21. The image sensor of claim 20, further comprising a voltage mode correlated double sampling unit connected to said sources of said readout transistors in said column or row of pixels through said addressing switch.