High dynamic range imager with a rolling shutter

• US 20080291313A1
• Filed: 06/10/2008
• Published: 11/27/2008
• Est. Priority Date: 08/27/2004
• Status: Active Grant

• Current Assignee: Alexander Krymski
• Original Assignee: Alexander Krymski
• Inventors: Krymski, Alexander
• Granted Patent: US 7,986,363 B2
• Time in Patent Office: Days
• US Class Current: 348/308
• CPC Class Codes: H04N 23/70 Circuitry for compensating brightness variation in the scene
• CPC Class Codes: H04N 23/741 by increasing the dynamic range of the image compared to the dynamic range of the electronic image sensors
• CPC Class Codes: H04N 25/00 Circuitry of solid-state image sensors [SSIS]; Control thereof
• CPC Class Codes: H04N 25/589 with different integration times, e.g. short and long exposures

Abstract

A high dynamic range imager operates pixels utilizing at least a short integration period and a long integration period. The pixel reading circuits of the imager are adapted to process pixel signals corresponding to the integration periods in parallel. The pixel signals are converted into digital values in parallel. The digital values are each linear functions of the incident light and therefore suitable for use with conventional color processing algorithms. A pipelined rolling shutter operation may be employed where the short integration period of one row of pixels is performed simultaneously with the long integration period of another row of pixels.

Claims

1-34. -34. (canceled)

35. An imaging circuit, comprising:

a pixel comprising a photodiode for photogenerating charge;

a first sample and hold circuit for receiving a first signal from a signal input node, said first signal representing an amount of charge photogenerated by said photodiode;

a second sample and hold circuit for receiving a second signal from said signal input node, said second signal representing an amount of charge photogenerated by said photodiode;

a third sample and hold circuit for receiving a third signal from said signal input node;

a first output circuit for receiving said first and third signals from said first and third sample and hold circuits; and

a second output circuit for receiving said second and third signals from said second and third sample and hold circuits.

36. The imaging circuit of claim 35, further comprising a bias circuit, coupled to said signal input node.

37. The imaging circuit of claim 36, wherein said bias circuit and said first, second, and third sample and hold circuits are coupled in parallel to said signal input node.

38. The imaging circuit of claim 35, wherein said first and second output circuits each comprise a differential amplifier.

39. The imaging circuit of claim 35, wherein said first signal is associated with a first integration period of said photodiode and said second signal is associated with a second integration period of said photodiode.

40. The imaging circuit of claim 39, wherein said second integration period is longer than said first integration period.

41. An imager, comprising:

a pixel array comprising a plurality of pixels arranged in a plurality of rows and a plurality of columns; and

a plurality of pixel reading circuits, each of said pixel reading circuits comprising;

a first, second, and third sample and hold circuits for respectively sampling and holding a reset signal, a first photo signal, and a second photo signal, from one of said plurality of pixels, said first and second photo signals representing charge generated by the same photodiode of said one of said plurality of pixels.

42. The imager of claim 41, further comprising:

an analog to digital conversion circuit for producing a first digital valve based on said first photo signal and a second digital value based on said second photo signal.

43. The imager of claim 42, wherein said analog to digital conversion circuit comprises:

a first analog to digital converter for producing said first digital value; and

a second analog to digital converter for producing said second digital value.

44. The imager of claim 42, further comprising:

an image processor coupled to said analog to digital conversion circuit, said image processor receiving said first and second digital values;

wherein said image processor

calculates a first result by performing linear arithmetic operations on said first digital value,

calculates a second result by performing linear arithmetic operations on said second digital value, and

calculates a third result by performing arithmetic operations on said first and second results.

45. The imager of claim 44, wherein said image processor performs color processing upon at least one of said first and second digital values.

46. The imager of claim 41, further comprising a controller coupled to said pixel array and said plurality of pixel reading circuits, wherein said controller operates said plurality of pixels over a short integration period and a long integration period.

47. The imager of claim 46, wherein said first photo signal is associated with said short integration period and said second photo signal is associated with said long integration period.

48. A system, comprising:

a processor; and

an imager coupled to said processor, said imager comprising;

a pixel array comprising a plurality of pixels arranged in a plurality of rows and a plurality of columns;

a plurality of pixel reading circuits, each of said pixel reading circuits comprising;

a first output circuit for producing a first pixel signal from a reset signal and a first photo signal, said first photo signal representing charge generated by a photodiode; and

a second output circuit for producing a second pixel signal from said reset signal and a second photo signal, said first photo signal representing charge generated by said photodiode.

49. The imager of claim 48 further comprising an analog to digital conversion circuit for respectively producing first and second digital values from said first and second pixel signals.

50. The imager of claim 49, wherein said analog to digital conversion circuit comprises:

a first analog to digital converter for producing said first digital value; and

a second analog to digital converter for producing said second digital value.

51. The imager of claim 49, further comprising:

an image processor coupled to said analog to digital conversion circuit, said image processor receiving said first and second digital values;

wherein said image processor

calculates a first result by performing linear arithmetic operations on said first digital value,

calculates a second result by performing linear arithmetic operations on said second digital value, and

calculates a third result by performing arithmetic operations on said first and second results.

52. The imager of claim 51, wherein said image processor performs color processing using at least one of said first and second digital values.

53. The imager of claim 50, further comprising a controller coupled to said pixel array and said plurality of pixel reading circuits, wherein said controller operates said plurality of pixels over a short integration period and a long integration period.

54. The imager of claim 53, wherein said first photo signal is associated with said short integration period and said second photo signal is associated with said long integration period.

55. A method for reading a pixel, comprising:

generating a first photo signal representing charge generated by a photodiode of said pixel during a first integration period;

generating a second photo signal representing charge generated by said photodiode of said pixel during a second integration period different than said first integration period;

forming a first output signal from said first photo signal; and

forming a second output signal from said second photo signal.

56. The method of claim 55, wherein said first and second output signals are concurrently formed.

57. The method of claim 55, further comprising:

digitizing said first output signal to produce a first digital value; and

digitizing said second output signal to produce a second digital value.

58. The method of claim 57, wherein said first and second output signals are concurrently digitized.

59. The method of claim 56, further comprising:

in each pixel of a pixel row,

forming a first pixel signal from said first photo signal and said reset signal; and

forming a second pixel signal from said second photo signal and said reset signal.

60. The method of claim 55, wherein said first and second integration periods have different lengths of duration.

61. The method of claim 57, further comprising:

performing linear arithmetic operations on said first and second digital values to respectively obtain a first and second intermediate results; and

performing arithmetic operations on said first and second intermediate results.

62. A method of operating an imager, comprising:

selecting a plurality of pixels of a pixel array, each of said pixels comprising a photodetector for generating charge in response to light and having an associated accumulation node for storing said charge;

in each of said plurality of pixels;

during said first integration period, storing a first amount of said charge at said associated charge accumulation node;

outputting a first photo signal representing said first amount of charge;

driving said charge accumulation node to a reset voltage and outputting a corresponding reset signal;

during a second integration period, storing a second amount of said charge at said associated charge accumulation node; and

outputting a second photo signal representing said second amount of charge;

wherein said step of driving said charge accumulation node is performed between said first and second integration periods.