DIGITAL SIGNAL RECEIVER WITH Q-MONITOR

• US 20080292026A1
• Filed: 08/14/2007
• Published: 11/27/2008
• Est. Priority Date: 08/25/2006
• Status: Active Grant

• Current Assignee: RPX Corporation
• Original Assignee: Alcatel-Lucent SA (Nokia Corporation)
• Inventors: PREISACH, Helmut
• Granted Patent: US 7,835,464 B2
• Time in Patent Office: Days
• US Class Current: 375/340
• CPC Class Codes: H04L 25/061 providing hard decisions only; arrangements for tracking or suppressing unwanted low frequency components, e.g. removal of dc offset removal of dc offset in coupling arrangements H04L25/029, H04L25/0296
• CPC Class Codes: H04L 7/0054 Detection of the synchronisation error by features other than the received signal transition by means of signal transition H04L7/033

Abstract

A digital signal receiver for a high-bitrate digital signal has a serial signal input (20, 20′) and a number of N parallel digital signal outputs (26) with N>1. The receiver contains at least N+1 digital sampling channels (31-35), a Q-monitor (37, 38) for comparing the output signal of at least two of said sampling channels (31-35), and a switch fabric (36) for controllably connecting N of said sampling channels (31-35) to said output leads (36) and at least two of said sampling channels (31-35) to said Q-monitor (37, 38). This allows to use N of the sampling channels to provide the N output signals while at the same time, the at least one remaining sampling channel can be used by the Q-monitor to scan an eye diagram.

Claims

1. A digital signal receiver for a high-bitrate digital signal comprising a serial signal input and a number of N parallel digital signal outputs with N>

1, the receiver further comprising at least N+1 digital sampling channels, a Q-monitor circuit for comparing the output signal of at least two of said sampling channels, and a switch fabric for controllably connecting N of said sampling channels to said output leads and at least two of said sampling channels to said Q-monitor.

2. A signal receiver according to claim 1, wherein the Q-monitor comprises an EXOR gate and an error counter.

3. A signal receiver according to claim 1, comprising D flip-flops connected between the switch fabric and the output leads.

4. A signal receiver according to claim 1, further comprising a microcontroller for configuring said switch fabric, for reading out pseudo error count values of said Q-monitor and for determining at least one optimized parameter for at least one of said sampling channels connected via said switch fabric to said Q-monitor.

5. A signal receiver according to claim 4, further comprising a variable gain amplifier and/or an electrical equalizer, wherein the microcontroller is adapted to adjust at least one operational parameter of said variable gain amplifier and/or electrical equalizer in dependence of pseudo error count values delivered by said Q-monitor.

6. A signal receiver according to claim 1, wherein said sampling channels are all of equal design comprising a sampler, a threshold/offset compensation, and a phase shifter.

7. A signal receiver according to claim 1, further comprising a clock recovery circuit for generating a recovered clock signal from said input signal.

8. A signal receiver according to claim 7, wherein said recovered clock signal has a clock rate of 1/N of the bitrate of said input signal.

9. A signal receiver according to claim 7 comprising a microcontroller adapted to adjust phase shifters in said N sampling channels connected via said switch fabric to said output leads such that these have phase values mutually shifted by 2π

/N.

10. A signal receiver according to claim 9, wherein said phase shifters receive from said clock recovery circuit at least two copies of said clock signal, mutually shifted by 90°

, wherein said phase shifters are adapted to create a phase shifted clock signal as a weighted sum of said at least two copies and wherein said microcontroller is adapted to adjust the phase shifters by adjusting their weighting factors.

11. A method of regenerating a high-bitrate digital signal and converting it to an N-bit wide parallel output signal with N>

1, comprising the steps of

providing at least N+1 sampling channels;

connecting N of said sampling channels to a parallel signal output;

connecting two of said sampling channels comprising the at least one remaining one to a Q-monitor;

using said Q-monitor to measure a one- or two-dimensional eye diagram of the at least one remaining sampling channel by varying a phase and/or threshold value thereof; and

repeating said steps using different assignment of sampling channels until eye-diagrams for all sampling channels have been measured.