Stress-Enhanced Performance Of A FinFet Using Surface/Channel Orientations And Strained Capping Layers

• US 20080296632A1
• Filed: 05/30/2007
• Published: 12/04/2008
• Est. Priority Date: 05/30/2007
• Status: Active Grant

• Current Assignee: Synopsys Incorporated
• Original Assignee: Synopsys Incorporated
• Inventors: Moroz, Victor, King Liu, Tsu-Jae
• Granted Patent: US 7,939,862 B2
• Time in Patent Office: Days
• US Class Current: 257/255
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

Different approaches for FinFET performance enhancement based on surface/channel direction and type of strained capping layer are provided. In one relatively simple and inexpensive approach providing a performance boost, a single surface/channel direction orientation and a single strained capping layer can be used for both n-channel FinFETs (nFinFETs) and p-channel FinFETs (pFinFETs). In another approach including more process steps (thereby increasing manufacturing cost) but providing a significantly higher performance boost, different surface/channel direction orientations and different strained capping layers can be used for nFinFETs and pFinFETs.

Claims

1. A FinFET comprising:

a source;

a drain;

a vertical channel connecting the source and the drain, the vertical channel forming a fin, the fin having a (100) surface orientation and a <

110>

channel direction orientation;

a gate straddling the fin; and

a compressive capping layer covering at least the fin and the gate to increase carrier mobility in the FinFET.

2. The FinFET of claim 1, wherein the compressive capping layer is silicon nitride.

3. The FinFET of claim 2, wherein the silicon nitride is between 40 nm and 100 nm thick.

4. The FinFET of claim 2, wherein the silicon nitride is approximately 50 nm thick.

5. The FinFET of claim 2, wherein the compressive capping layer of silicon nitride has approximately 2.5 GPa compressive stress.

6. The FinFET of claim 1, wherein the FinFET transistor is an nFinFET and the compressive capping layer increases electron mobility.

7. The FinFET of claim 1, wherein the FinFET transistor is a pFinFET and the compressive capping layer increases hole mobility.

8. An integrated circuit (IC) including a plurality of FinFETs, each FinFET comprising:

a source;

a drain;

a vertical channel connecting the source and the drain, the vertical channel forming a fin, the fin having one of a (100) surface orientation and a (110) surface orientation, the fin also having one of a <

100>

channel direction orientation and a <

110>

channel direction orientation;

a gate straddling the fin; and

a strained capping layer covering at least the fin and the gate to increase carrier mobility in the FinFET,

wherein fins of nFinFETs have the (100) surface orientation and the <

100>

channel direction orientation, and the strained capping layer of the nFinFETs is a tensile capping layer, and

wherein fins of pFinFETs have the (110) surface orientation and the <

110>

channel direction orientation, and the strained capping layer of the pFinFETs is a compressive capping layer.

9. The IC of claim 8, wherein the strained capping layer for the nFinFETs and the pFinFETs is silicon nitride.

10. The IC of claim 9, wherein the silicon nitride is between 40 nm and 100 nm thick.

11. The IC of claim 9, wherein the silicon nitride is approximately 50 nm thick.

12. The IC of claim 9, wherein the compressive capping layer has approximately −

2.5 GPa compressive stress and the tensile capping layer has approximately +2.5 GPa tensile stress.

13. A method of manufacturing FinFETs to enhance carrier mobility, the FinFETs including both nFinFETs and pFinFETs, the method comprising:

forming a fin of each FinFET with a (100) surface orientation and a <

110>

channel direction orientation;

forming a gate over the fin; and

forming a compressive capping layer over the gate and the fin.

14. The method of claim 13, wherein the compressive capping layer is silicon nitride.

15. The method of claim 14, wherein the silicon nitride is deposited between 40 nm and 100 nm thick.

16. The method of claim 14, wherein the silicon nitride is deposited approximately 50 nm thick.

17. The method of claim 14, wherein the compressive capping layer of silicon nitride provides approximately 2.5 GPa compressive stress.

18. A method of manufacturing an integrated circuit (IC) including a plurality of FinFET transistors, each FinFET transistor comprising a source, a drain, and a vertical channel connecting the source and the drain, the vertical channel forming a fin, the method comprising:

forming the fins of nFinFETs with a (100) surface orientation and a <

100>

channel direction orientation;

forming the fins of pFinFETs with a (110) surface orientation and a <

110>

channel direction orientation;

forming gates to straddle the fins; and

forming strained capping layers to cover at least the fins and the gates to increase carrier mobility in the FinFETs,

wherein the strained capping layer of the nFinFETs is a tensile capping layer, and

wherein the strained capping layer of the pFinFETs is a compressive capping layer.

19. The method of claim 18, wherein the strained capping layer for the nFinFETs and the pFinFETs is silicon nitride.

20. The method of claim 19, wherein the silicon nitride is between 40 nm and 100 nm thick.

21. The method of claim 19, wherein the silicon nitride is approximately 50 nm thick.

22. The method of claim 19, wherein the compressive capping layer has approximately −

2.5 GPa compressive stress and the tensile capping layer has approximately +2.5 GPa tensile stress.