Integrated circuit structures with multiple FinFETs

• US 20080296702A1
• Filed: 05/30/2007
• Published: 12/04/2008
• Est. Priority Date: 05/30/2007
• Status: Active Grant

• Current Assignee: Advanced Manufacturing Innovations Incorporated
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lee, Tsung-Lin, Yang, Fu-Liang, Liu, Sheng-Da, Chang, Chang-Yun
• Granted Patent: US 8,174,073 B2
• Time in Patent Office: Days
• US Class Current: 257/401
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate

Abstract

A semiconductor structure includes a semiconductor substrate; and a first Fin field-effect transistor (FinFET) and a second FinFET at a surface of the semiconductor substrate. The first FinFET includes a first fin; and a first gate electrode over a top surface and sidewalls of the first fin. The second FinFET includes a second fin spaced apart from the first fin by a fin space; and a second gate electrode over a top surface and sidewalls of the second fin. The second gate electrode is electrically disconnected from the first gate electrode. The first and the second gate electrodes have a gate height greater than about one half of the fin space.

Claims

1. A semiconductor structure comprising:

a semiconductor substrate;

a first Fin field-effect transistor (FinFET) at a surface of the semiconductor substrate, the first FinFET comprising;

a first fin; and

a first gate electrode over a top surface and sidewalls of the first fin; and

a second FinFET at the surface of the semiconductor substrate, the second FinFET comprising;

a second fin spaced apart from the first fin by a fin space; and

a second gate electrode over a top surface and sidewalls of the second fin, wherein the first and the second gate electrodes have a gate height greater than about one half of the fin space.

2. The semiconductor structure of claim 1, wherein the first and the second fins are on a first and a second active region in the semiconductor substrate, respectively, and wherein the semiconductor structure further comprises an insulating region horizontally adjoining the first and the second active regions.

3. The semiconductor structure of claim 1, wherein the first and the second fins are on a buried oxide.

4. The semiconductor structure of claim 1, wherein the fin space is less than about 80 nm.

5. The semiconductor structure of claim 1, wherein the first and the second fins have a fin height, and wherein the fin space is less than about two times the fin height.

6. The semiconductor structure of claim 5, wherein the fin height is greater than about 25 nm.

7. The semiconductor structure of claim 1, wherein the sidewalls of the first and the second fins have tilt angles of greater than about 87 degrees.

8. The semiconductor structure of claim 1, wherein the first FinFET further comprises:

a gate dielectric between the first fin and the first gate electrode; and

a source/drain region physically connected to the first fin.

9. The semiconductor structure of claim 8, wherein the source/drain region comprises a material selected from the group consisting essentially of SiGe and SiC.

10. The semiconductor structure of claim 8, wherein the source/drain region has a width greater than a width of the first fin.

11. A semiconductor structure comprising:

a semiconductor substrate;

an insulating region in the semiconductor substrate;

a first active region and a second active region on opposite sides of the insulating region;

a first fin and a second fin on the first and the second active regions, respectively, wherein the first and the second fins have a fin space therebetween, and have a fin height;

a first and a second gate dielectric on sidewalls and top surfaces of the first and the second fins, respectively;

a first and a second gate electrode on the first and the second gate dielectrics, respectively, wherein the first and the second gate electrodes have a gate height, and wherein the fin space is less than at least one of two times of the gate height and two times of the fin height;

a first source region and a first drain region on opposite sides of the first fin; and

a second source region and a second drain region on opposite sides of the second fin.

12. The semiconductor structure of claim 11, wherein the fin space is less than both two times of the gate height and two times of the fin height.

13. The semiconductor structure of claim 11, wherein the first source and the first drain regions have widths greater than a width of the first fin.

14. The semiconductor structure of claim 11, wherein the substrate is a bulk substrate, and wherein the first source and the first drain regions have a junction depth less than the first fin height, and wherein the second source and the second drain regions have a junction depth less than the second fin height.

15. The semiconductor structure of claim 11 further comprising first silicide regions on the first source and the first drain regions, and second silicide regions on the second source and the second drain regions, wherein the first and the second silicide regions each have heights less than respective junction depths of the respective first and the second source and drain regions.

16. The semiconductor structure of claim 11, wherein the first source and the first drain regions comprise a material selected from the group consisting essentially of SiGe and SiC.

17. The semiconductor structure of claim 11, wherein the fin space is less than about 80 nm.

18. The semiconductor structure of claim 11, wherein the first and the second fins each have a tilt angle of greater than about 87 degrees.

19. The semiconductor structure of claim 18, wherein the first and the second fins each have a tilt angle of greater than about 90 degrees.

20. A semiconductor structure comprising:

a semiconductor substrate;

a first Fin field-effect transistor (FinFET) at a surface of the semiconductor substrate, the first FinFET comprising;

a first fin; and

a first gate electrode over a top surface and sidewalls of the first fin; and

a second FinFET at the surface of the semiconductor substrate, the second FinFET comprising;

a second fin spaced apart from the first fin by a fin space; and

a second gate electrode over a top surface and sidewalls of the second fin, wherein the first and the second gate electrodes have a gate height greater than about one half of the fin space, and wherein the fin space is less than about 80 nm.