SYSTEMS AND METHODS FOR ENHANCING PERFORMANCE OF A COPROCESSOR

• US 20080301687A1
• Filed: 07/14/2008
• Published: 12/04/2008
• Est. Priority Date: 02/18/2003
• Status: Active Grant

• Current Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Original Assignee: Microsoft Corporation
• Inventors: Gosalia, Anuj B., Pronovost, Steve
• Granted Patent: US 9,298,498 B2
• Time in Patent Office: Days
• US Class Current: 718/103
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: G06F 9/461 Saving or restoring of program or task context
• CPC Class Codes: G06F 9/4843 by program, e.g. task dispatcher, supervisor, operating system
• CPC Class Codes: G06F 9/5016 the resource being the memory
• CPC Class Codes: G06F 9/5038 considering the execution order of a plurality of tasks, e.g. taking priority or time dependency constraints into consideration scheduling strategies G06F9/4881 and subgroups
• CPC Class Codes: G06F 9/544 Buffers; Shared memory; Pipes
• CPC Class Codes: G06F 9/546 Message passing systems or structures, e.g. queues
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Techniques for minimizing coprocessor “starvation,” and for effectively scheduling processing in a coprocessor for greater efficiency and power. A run list is provided allowing a coprocessor to switch from one task to the next, without waiting for CPU intervention. A method called “surface faulting” allows a coprocessor to fault at the beginning of a large task rather than somewhere in the middle of the task. DMA control instructions, namely a “fence,” a “trap” and a “enable/disable context switching,” can be inserted into a processing stream to cause a coprocessor to perform tasks that enhance coprocessor efficiency and power. These instructions can also be used to build high-level synchronization objects. Finally, a “flip” technique is described that can switch a base reference for a display from one location to another, thereby changing the entire display surface.

Claims

1. A method for scheduling tasks for processing in a coprocessor, comprising:

generating a run list comprising a list of tasks for processing by a coprocessor, wherein the run list is generated by a central processing unit (CPU);

delivering the run list to a scheduler process, wherein the scheduler process prepares the tasks on the run list for processing by a coprocessor; and

processing the tasks by the coprocessor in an order indicated by the run list, wherein if a switching event occurs when processing one of the tasks, the coprocessor switches immediately to the next task on the run list.

2. A method according to claim 1 wherein the coprocessor is a graphics processing unit (GPU).

3. The method of claim 1 wherein a switching event comprises at least one of a completion of processing a previously submitted task, a page fault in processing a task, a general protection fault in processing a task, and a request by the CPU to switch to a new run list.

4. The method of claim 1, further comprising signaling the CPU with an interrupt signal when the coprocessor switches from one task in the run list to the next task in the run list, wherein when the CPU receives the interrupt signal, the CPU builds a new run list for the coprocessor.

5. The method of claim 1, further comprising generating a second run list by the scheduler process, whereby the scheduler process can initiate a change in the order of tasks to be processed by the coprocessor.

6. The method of claim 5, further comprising prohibiting a first task of a first run list from appearing in the second run list.

7. The method of claim 5, further comprising prohibiting a second task of a first run list from appearing in the second run list unless it is a first task of the second run list.

8. The method of claim 1, further comprising storing information regarding the history of coprocessor switches from task to task in a specified system memory location readable by the scheduler.

9. The method of claim 8 wherein the system memory location readable by the scheduler is a history buffer available to a single coprocessor only.

10. The method of claim 8 wherein the history buffer comprises sufficient memory to store at least twice the amount of information required to store the run list.

11. The method of claim 8, further comprising specifying a coprocessor write pointer, which indicates a location in the history buffer where the coprocessor can write new information.

12. A computer readable medium comprising computer executable instructions for carrying out the method of claim 1.

13. A modulated data signal carrying computer executable instructions for use in performing the method of claim 1.

14. A computing device comprising means for performing the method of claim 1.